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[SOLVED] How does this circuit start up? D flip flops for phase frequency detection

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amsdesign

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This is a CMOS D Flip flop courtesy Razavi.

Razavi_DFF.JPG

The circuit is made up of NOR gates.

But if you try to work out by pen and paper when Reset is 0 and CK is 1 you will find you can't really find out what Q is. Does this circuit need some additional star-up circuitry?

Update : If I combine two of these circuits in the form of a phase frequency detector as shown below, the circuit works correctly. How is this happening?

pfd.png


:thinker:
 

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FvM

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In usual terminology, a D-FF is an edge triggered device. Technically it's implemented as a combination of two latches, see the circuit from a HC74 datasheet.

dff.png

The "DFF" shown in your post isn't edge triggered and can't work for a phase-frequency detector.
 

amsdesign

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Hi FvM,

The individual simulation of this block shows it's a falling edge triggered block.
I set Reset to 0 and have supplied a clock pulse of 1us period. And this is the output.


dff_out.JPG

A is the clock.
QA is the output
net_06 is reset
 

FvM

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I don't see how the simulation waveform fit's the circuit. CK is obviously setting Q if CK =1 and Reset = 0.

I have to correct my previous statement. The circuit works like an edge triggered DFF with constant D=1, because the reset input is latched as long as ck inout is high. So a PFD made of two of these blocks and an AND gate should work.
 

amsdesign

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Hi FvM,

So this circuit works as a edge-triggered DFF with D=1 right? But how do I visualize that in this drawing below? I want to manually see the 1's and 0's setting Q to 1. If clock is 1 what is next to set Q=1?

Razavi_DFF.JPG
 

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I have no problem to trace circuit operation on pencil and paper.

A rising CK edge sets Q if Reset is low. A high level of Reset resets Q. To release the reset state, CK must be turned low, which causes the intended edge sensitive behaviour.
 

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I have no problem to trace circuit operation on pencil and paper.

A rising CK edge sets Q if Reset is low. A high level of Reset resets Q. To release the reset state, CK must be turned low, which causes the intended edge sensitive behaviour.


If Reset is 0. I don't know the output of the 4th NOR gate.
If clock is 1, the output of the first NOR gate is 0 which is the input of the second NOR gate. The output of the second NOR gate is Q.
So how do you obtain the second input of the second NOR gate to obtain Q?
Once again, in the figure I put ?

I can trace the circuit's behaviour if Reset is 1 though.
 

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A logic circuit with internal state memory may have an unknown initial state, just a trivial fact.

To start the simulation from a known state, set CK = 0 and apply a reset pulse. Reset = 1, Reset = 0.
 

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A logic circuit with internal state memory may have an unknown initial state, just a trivial fact.

To start the simulation from a known state, set CK = 0 and apply a reset pulse. Reset = 1, Reset = 0.

Cool. Thank you so much :smile:
 

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