How does the read and write address work in dual port RAM for FIFO?

[chikaofili]

Hello,
I am trying to perform 3x3 kernel image convolution by using 2 FIFO and 3 shift registers so that I can implement a pipelined fifo

I will prefer not to use the FIFO ipcore in Altera but I dont know how the dual port ram can be used as an FIFO.

I guess my question is ' can someone explain how the read and write address works in dual port ram for FIFO.


Thank u

 

[soloktanjung]

Re: FIFO (Dual port ram)

Please look at this example code designing a synchronous read/write FIFO by instantiating a dual port RAM: Synchronous FIFO