How does the D flip-flop work?

[mYthorON]

I don't know how the D flip-flop work exactly?
Anybody can give me a glue about that. Thanks.

 

[mYthorON]

Question 2:

How to implement this D-ff with Verilog?

Thanks.

 

[no_mad]

Hi,

D-FF is a storage element.
FF is an edge triggered. Meaning, in the example below, every +ve edge of clk input will pass to output.

Q2:
// D ff with sync reset
module dff3 (clk, reset, d2, d1, d0, q2, q1, q0);

input clk, reset, d2, d1, d0;
output q2, q1, q0;

reg q2, q1, q0;

always @(posedge clk)
begin
if (reset)
begin
q2 <= 0;
q1 <= 0;
q0 <= 0;
end

else
begin
q2 <= d2;
q1 <= d1;
q0 <= d0;
end

end

endmodule

Hope it helps

 

[nafaiz]

d-flip-flop(DFF)'s characteristic

D(0,1,2) =0 Q(0,1,2)(t+1)=0 operation= reset
D(0,1,2) =1 Q(0,1,2)(t+1)=1 operation= set

This means that the DFF output will be 1 whenever the condition was set(D=1).

there is no input in to the DFF that produces a "no change" condition. This condition can be accomplished either by disabling the clock pulses or by leaving the clock pulses undisturbed and connecting the output back into the D input using a multiplexer when the state of the DFF must remain the same.



DFF excitation table:

Q(t)=0 Q(t+1)=0 D=0
Q(t)=0 Q(t+1)=1 D=1
Q(t)=1 Q(t+1)=0 D=0
Q(t)=1 Q(t+1)=1 D=1

 

[bismillah]

Hi,
Basically D-FF is a delay element, and it send whatever is applied at the input to the output at the clock edge.

 

[checkmate]

The DFF is a storage element. It stores its value on its output. Its output value is updated with the input value at every clock edge (either rising or falling). It is an important element because it allows for synchronous circuits, ie where value changes are synchronized with clocks.