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How does setup margin affect the timing?

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hrushitha

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hi all,
can any one tell me about the setup margin.how it effect the timing.
if i change setup margin from 0.5 to 0.6,what will happend
please help me
thanks
 

rameshsuthapalli

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setup margin

Hi,

i am nopt getting how u r specifing the setup time for a design.is it clock unsertinity.explain clearly such that i can help u.

regards,
ramesh.s
 

srkumar81

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Re: setup margin

Usually setup margin is given for tolerating the difference seen in P&R tool and STA tool. This is like introducing some pessimism in P&R tool so that we can close the design with some 100ps setup or hold margin.
Regarding timing it means we are closing the design with less slack. sometimes many paths will be violating if we increase the setup margin.
 

xinsu

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setup margin

if you only use setup margin in timing opt but remove in STA,this is used for overconstraint to opt,if used this in STA,maybe take fabracation into account.
 

pratap_v

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Re: setup margin

If setup margin is 0.4 then u r making the tool to optimise all the the paths untill the slack is 0.4
 

vipulsinha

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setup margin

See when you synthesize the dsign and see the synthesis report you will find that net delay also come into picture. setup margin increase will allow better timing as the margin time is increase. What we mean by it is we have .5 time unit more that the circuit will show setup time violation.
 

funster

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Re: setup margin

design is a iteration and sub-optimal process,

it's all up to your situation to make decision.



hrushitha said:
hi all,
can any one tell me about the setup margin.how it effect the timing.
if i change setup margin from 0.5 to 0.6,what will happend
please help me
thanks
 

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