Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
try referring Razavi.... there are lot of ieee papers here in board regarding pipelined adc,... they can be valuable info.... actually i'm working on it too.... and got a lot of papers from here...
arrange digital(dec) and analog(stage/tha) apart and use guarding ring to sepearate.
reference should be arraged local if power is not a issue.
watch matching issue of tha and mdac, keep summing node of opamp around clean.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.