How does multiplexing SDO and SDI work in SPI with MCP4131 <-> PIC MCU?

[matrixofdynamism]

(1) How can SPI multiplex SDI and SDO and use same pin for both since data is only clock at a single edge on both pins? I read the datasheet for MCP4131 for the first time and have been introduced to the concept of multiplexing SDI and SDO. The datasheet gives diagram for how this component maybe connected to a microcontroller on pg.41 of the datasheet.

(2) Since the same edge is usually used for SDO and SDI, doesn't that mean that I will just be reading the data that I am writing out anyway? What am I missing here? I do see the resistor that is connected between SDO and SDI and the note that says "R1 must be sized to ensure VIL and VIH of the devices are met.". But this still does not give me a feeling of this will actually work.

(3) Does PIC actually support multiplexed SDI and SDO of SPI or is using software SPI i.e bit banging the only possibility that exists?

 

[Easyrider83]

1. The same way as you work with normal 3-lines SPI. After receiving read comand, SDIO switches from tri-state to push-pull and shift out the data.
2. First received byte will be equal to byte was send.
3. Any mcu's support it. Just connet MOSI throught the resistor 1-10k.

 

[matrixofdynamism]

Re: How does multiplexing SDO and SDI work in SPI with MCP4131 &amp;lt;-&amp;gt; PIC MCU?

OK, I think there is a confusion here. I am thinking that multiplexing means that the single pin shall input and output data during the same transfer i.e once start sending SCK signal to the device, for a few SCK cylces it shall take the data in and then for remaining SCK cycles it shall give the data out. e.g a 16 cycle transfer, 5 bits the peripheral takes in then 8 bits it outputs and then remaining 3 bits it takes as input again.

Is this how it works?

Since if only data read or only data write can take place at one time, then the story is very different here. Thus in the above example we can only either write those 5 bits at start and then 3 bits at end of the write cycle, and then seperately read the output from the device. This way there shall be different commands issued for reading and writing from the microcontroller's side.

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I have attached the SPI timing waveforms. Looking at them it is clear that both SDO from the peripheral chip and SDO from the microcontroller side are driven simultaneously.

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OK, I have studied the structure that connects the two sides via a 10kohm resistor. I understand that the resistor prevents the output from microcontroller SDO from being applied to the microcontroller SDI directly. If the peripheral chip pulls the line low, the SDI of the microcontroller shall see 0V even if the microcontroller SDO is 5V. If the peripheral chip uses its "smart" internal pull up as it says in the datasheet, then the SDI of the microcontroller shall se a 5V even if the microcontroller's SDO is 0V. And thus, multiplexing works.

My question the becomes:

If the SDO of mirocontroller is 0V and and the peripheral chip SDI/SDO becomes SDO and lets its internal pull-up work, then the line shall be at 5V. This means that a 5V is being applied to the SDO externally via a 10kohm resistor. Thus, this means that a current of 0.5mA shall have to flow into the SDO of the PIC. So is the SDO of the PIC capable of sinking this amount of current? Is this why a big resistor must be chosen so the microcontroller SDO does not corrupt the SDO from the peripheral chip?