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How does inout pin declaration in VHDL work?

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alexz

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When a pin is declared as the inout type, how does it know when to implement is as an input and when as an output?
 

EDALIST

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inout vhdl

you always need some control pin to dictate the usege of the pin.
whether its a direction selection control signal , or output enable or read/write- signal.
 

keano

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inout in vhdl

please can u explain more ?
 

vivek

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vhdl inout example

you usually use a tristate buffer for handling inout ports. you will have an enable signal for controlling it.
 

alexz

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vhdl inout signal

It does not work on both directions.
I have tried to simulate a tri state buffer, and it works only as an output
 

vivek

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vhdl inout port

i dont speak vhdl very well, will give u how itz done in verilog.

suppose ur inout signal is inout_sig which lets say is a bit, then in the top file of ur design :

assign inout_sig = (out_en) ? out_sig : 1'bZ;

The above statement infers a tristate where out_sig is its input and out_en is the enable. when out_en = 1, out_sig is driven to inout_sig, otherwise when out_en = 0 it will be in high impedence. then any value that is driven to the inouot_sig as an input (from ur testbench) can be taken. for getting the input, u should have an input wire which should be connected to inout_sig.

here out_sig shall be a wire declared as output. whenever u want to drive a data to ur inout port, assert the out_en to 1 and drive the data to the out_sig wire.
now according to the assign statement, inout_sig will have the value you drive.

The same concept can be done in VHDL. Hope this helps .. :D[/img]
 

Iouri

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vhdl tristate

it is alos depends how you did your test bench in some case stimul can force pin to show fixed value. here the VHDL example how to impliment biderectional pin


pin_io <= a when enable = '1' else z;---- output data
-- input data

process(clk)
begin
if clk = '1' and clk'event than

Added after 1 minutes:

it is alos depends how you did your test bench in some case stimul can force pin to show fixed value. here the VHDL example how to impliment biderectional pin


pin_io <= a when enable = '1' else z;---- output data
-- input data

process(clk)
begin
if clk = '1' and clk'event than
if latch = '1' than
q <= pin_io;
end if;
end if;
end process;


Good lack
 

kgeorge123

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inout port in vhdl

Ok First of all you will have to explain is this a pin of a chip or a port of an entity??

If we assume that it is a pin of a chip then then you will have an IO cell interfaced with this port of the top level entity in VHDL. Now this IO cell will have a feedback tristate buffer with one input . And the tristate will activate only when signal one is driving.Basically the enable of tristate will be controlled by signal one.In other case when Pin1 is being sourced from outside signal two will be directly assigned its value.

Pin1--------------<|---- Signal One (output)
Pin1-------------- >> Signal Two(input)
 

tkbits

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vhdl tristate buffer

alexz said:
It does not work on both directions.
I have tried to simulate a tri state buffer, and it works only as an output
The tristate buffer is not a signal.
The tristate buffer is a component whose output connects to a signal.

Several tristate buffers can have their outputs tied together. This is reflected in usage like the following:

-- the following four lines are written in the same architecture
DBUS <= REGA when REGA_READ = '1' else (others => 'Z');
DBUS <= REGB when REGB_READ = '1' else (others => 'Z');
DBUS <= REGC when REGC_READ = '1' else (others => 'Z');
DBUS <= PORTA when PORTA_READ = '1' else (others => 'Z');

Each expression on the right is a tristate buffer. The signal on the left is what the output of the buffer is connected to. Note what I didn't say: I didn't say that DBUS is the output of a tristate buffer.

To get valid DBUS signals, 1) all outputs must be from tristate buffers, and 2) exactly one output must be active (non-Z).

That's the simple rule. We could complicate things by adding weak logic. But for FPGA work, this should be sufficient.
 

nee_naresh04

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vhdl tri-state

well i think u will understand by this example...

when ever u use some output pins which are again feed back to ur input side then we generally use inout pins..

for example

use library;
use ieee.std_logic_1164.all;
entity sr_latch is
port( s,r : in std_logic;
q,qb : inout std_logic);
end sr_latch;

archetecture behv of sr_latch is
begin
q <= s nand qd;
qb <= r nand q;
end behv;


in case of the above example ( sr latch)..we take qb output pin to again as an input pin at the nand gate input...this is where inout pin we use generally...
 

alexz

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vhdl signal inout

tkbits said:
To get valid DBUS signals, 1) all outputs must be from tristate buffers, and 2) exactly one output must be active (non-Z).

.


If the DBUS is inout type of a port, how can one output be active?
It should be the case where none of the tri state buffers are active at some point.
 

tkbits

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vhdl inout

The above rules are for VALID (non-X) signals. It is possible to have no tristate outputs active, in which case your signal has an unknown value. It is possible to have more than one tristate output active - if there are opposing outputs (one at '0' and another at '1'), the signal will also have an unknown value.

You guarantee having VALID signals at a given moment by ensuring exactly one output is active at that time (and satisfying the setup time of all inputs tied to it).

You can't look at the inout port in isolation from the external logic. The external logic outputs must also connect via tristate outputs to the inout port, to allow signals to be output from within the module.
 

alexz

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vhdl inout pin

So, I am taking the default uotput should be TRI STATE right?
 

tkbits

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vhdl inout buffer

That is good design.
 

pgadde1

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Re: vhdl inout pins

Hi am trying to do something similar here in vhdl

I am taking a output from a component and its giving me the correct output But when I try to feedback it it back to the input its not working.

EX:
input in std_logic_vector = "1110" ---some constnt value
sel : inout std_logic_vector (2 down to 0) : = "00" --intialization
L1 : component port map mux41 (inp,sel,output1);

L2 : component port map mux41 (inp,sel,output2);

-- feedback process
process

variable q : std_logic_vector(3 downto 0);
begin
q := output1 & output 2;
sel <= q;
final output <= q;
wait for 10 ns;
end process;


When I look at the fianl output without the feedback process it is 01

input: 1110
sel : 0X -> according to my mux logic it should be 1
final output: 0X

Req output

input :0010
sel : 00
final output :01

2nd clock cycle: 0010
sel: 01
fianloupt: 10... like a cycle 00->01->10 ->11


I dont unstand why is it showing X instead of 1 any help??????????????

well i think u will understand by this example...

when ever u use some output pins which are again feed back to ur input side then we generally use inout pins..

for example

use library;
use ieee.std_logic_1164.all;
entity sr_latch is
port( s,r : in std_logic;
q,qb : inout std_logic);
end sr_latch;

archetecture behv of sr_latch is
begin
q <= s nand qd;
qb <= r nand q;
end behv;


in case of the above example ( sr latch)..we take qb output pin to again as an input pin at the nand gate input...this is where inout pin we use generally...
 

mrflibble

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X generally means you forgot to initialize your registers to a specific value. So either use an init value for registers, OR assert the reset in your modules.
 

pgadde1

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X generally means you forgot to initialize your registers to a specific value. So either use an init value for registers, OR assert the reset in your modules.

Yeah u are right am trying to intialize inout pins the same way as in pins in both .vhdl and test bench but its showing UUUU.

Syntax am using
Sel inout std_logic_vectors := "00"
 

mrflibble

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I doubt the inout is going to work that way...

My vhdl skill is virtually non-existent so I´d better give you a random link: https://www.altera.com/support/examples/vhdl/v_bidir.html

And then in your testbench you need to make sure the data and the direction registers get an initial value. After that your inout and everything else should be peachy!
 

pgadde1

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I wonder why everybody left vhdl!! Thankyou so much for your time.


QUOTE=mrflibble;1119901]I doubt the inout is going to work that way...

My vhdl skill is virtually non-existent so I´d better give you a random link: https://www.altera.com/support/examples/vhdl/v_bidir.html

And then in your testbench you need to make sure the data and the direction registers get an initial value. After that your inout and everything else should be peachy![/QUOTE]
 

mrflibble

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I wonder why everybody left vhdl!!

I seriously doubt that. There´s quite a few people on this board that are pretty good at vhdl. I just happened to have chosen verilog as starting point because it was easier for me as self study hdl language.
 

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