Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How does affect as incremental to synthesis?

Status
Not open for further replies.

u24c02

Advanced Member level 1
Advanced Member level 1
Joined
May 8, 2012
Messages
404
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Visit site
Activity points
4,101
Hi.
I wondering about How does affect as incremental to synthesis?

I have 2 library about rvt, hvt.

If I use only rvt for synthesis including clock insertion at the first then I re-compile use option the -inc use with only hvt library and scan insertion.

Then I wonder about clock insertion latch is able to change by hvt library at second re-compile time?

My question is that what if I use recompile with -inc then is this affect the first compiled net?
For example, at the first time I just use rvt library for the first compile then I use hvt at the second compile.

In my experiment, there are difference results.
Case 1.
First use hvt then rvt.
Case2.
First use rvt then hvt.
Case3.
First use hvt rvt all.

There are difference what the HVT RVT ratio as case.
Also I just wondering about what should I do for finding the better methods.
 

I think, You can set as a dont touch attribute to particular those clock insertion latch cells during second compile i.e. incrimental compile.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top