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How does a AGC amplifier work?!

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Anachip

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agc single op amp

Hi Guys,

I'm currently doing research on the AGC (Automatic Gain Control) Amplifer. While reading journals, i came to know that the AGC is consists of a Peak Detector, Comparator, Lossy Integrator and Low Pass Filter. I found out one circuit a part of AGC design which is comparator, integrator and low pass filter as per attached. But i'm still can't understand how does this circuit works. What must the value of Rf, Cf, Ro & Co to be designed if im desiging this circuit to work at 1.25Gbps. In the initial design, what is the dc voltage I need to set at the Vagc output. I'm connecting this Vagc output to the gate of NMOS which is parrallel with a resistor in order to control the gain. Meaning that, when my Vpeak is higher than my refernce voltage, my Vagc need to go high, thus it will turn the NMOS and the total gain will be reduced and vise versa. Please guide me to understand how to design this circuit. Thank you very much.

Anachip.
 

pixel

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opamp agc schematic

Comparator (M1-M9) in the form of standard symetrical CMOS OTA, just amplifies the differnce between Vpeak and Vref.
M12 acts as integrator amplifier. Input is OTA output current, which is integrated (low passed through Rf Cf). Ro, Co is output low pass filter.
Output dc point should be made that NMOS is off. Point where you turn on NMOS is dictated by Vref.


Value of elements depends on your system - do you have to detect first impulse or you have some synhronization bits. Are signals always present (i.e 101010 when you have not data), or you have data transfer in bursts. Do you have large number of 11111 or 0000, ...
So it is a tough task, and usually need lot of effort.
 

vsgiri

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Question On AGC Design!!

First fix the bias voltage of agc_out. This is based on the NMOS and the resistor in parallel. When Vpeak = Vref, your AGC should give a certain gain. The voltage required at the gate of the NMOS for this gain should be the bias voltage at agc_out.

To my understanding, Rf, Cf are for frequency compensation - correct me if I'm wrong. You need to ensure positive phase margin with these two.

Ro, Co are the output low pass filter. Remember the Cgs of the NMOS which comes in parallel.

Giri
 

pixel

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Re: Question On AGC Design!!

vsgiri said:
To my understanding, Rf, Cf are for frequency compensation - correct me if I'm wrong. You need to ensure positive phase margin with these two.

Giri

Miller compensation has the sense in the case of two stage OP amps with dominant and non-dominant pole. OTA is one stage with only one pole and there is no need for compensation...
 

vsgiri

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Question On AGC Design!!

You are absolutely right, Pixel about Miller compensation. In an OTA most of the nodes are low impedances.

But I'm still not clear about the function of Rf and Cf. You mentioned it would low pass filter. But I feel it would have a differentiator kind of effect because it comes in series. Moreover, my simulations confirm that.
Could you clarify this for me?

Giri
 

pixel

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Re: Question On AGC Design!!

vsgiri said:
You are absolutely right, Pixel about Miller compensation. In an OTA most of the nodes are low impedances.
But I'm still not clear about the function of Rf and Cf. You mentioned it would low pass filter. But I feel it would have a differentiator kind of effect because it comes in series. Moreover, my simulations confirm that.
Could you clarify this for me?

Giri

M12 common source with active mirror -> high gain.

If you look at mos M12 as ideal OP you have Cf between output and input - i.e integrator...
Input to MOS is current from OTA:

Transfer characteristic
Without Rf H(s)=V/I=1/SCfRf - Intergrator
With Rf H(s)=(Rf/1+SCfRf) - Low pass, with bandwidth 1/2piRfCf !!!
+
Output filter: 1/(1+sCoRo)

-> you have to set Q factor.
 

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Re: Question On AGC Design!!

Hi Pixel,
In an OTA, we don't have the common source amplifier and its current source load.
Thus the output node is the only dominant pole.
Now we have this node and the final output node,(the output of the constant current source amplifier), as dominant poles. They are both high impedance nodes,and can come quite close.
This can lead to problems at high frequencies.
The capacitor connecting input and output is a typical Miller Capacitor.
Isn't this exactly similar to two stage opamp?
Why all this trouble?
Why not directly implement a 2 stage opamp?
I have already done SPICE simulations to back my statements.
I got negative phase margin and with Cf I'm able to get back to positive phase margin.
Also, I'm not clear with your transfer functions H(S)=V/I. that is a trans resistance right?
Transfer characteristic
Without Rf H(s)=V/I=1/SCfRf - Intergrator
With Rf H(s)=(Rf/1+SCfRf) - Low pass, with bandwidth 1/2piRfCf !!!
+
Output filter: 1/(1+sCoRo)

-> you have to set Q factor.

I may be wrong big time, so if you could be throw more light, it would be just great!

Giri
 

pixel

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Re: Question On AGC Design!!

That MOSFET is not part of the OTA. It is just next stage.
 

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Question On AGC Design!!

Yes, transistors M1-M9 form the OTA. M11,M12 form the common source amplifier with current source load. It is this output node along with the OTA output node that are now two high impedance nodes.
So, what are you trying to say?

Giri
 

pixel

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Re: Question On AGC Design!!

<OK,my fault.
When you make global feedback, like in AGC this configuration acts like Miller compensation. Dominant pole is at the output of OTA. Another pole is at the output, and it should be far enough in order to maintain stability.
 

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Question On AGC Design!!

Yes. Thanks for clearing the doubt.

Giri
 

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Re: Question On AGC Design!!

If it is unstable try to lower loop OTA gain, for example make output OTA MOSFET M7, M9to be 4x smaller than M3, M4.
Rf is used to make smaller resistance at the MOSFET output, which have effect that Cout see (Rout +Rf/gm). For too large Rf you will have problem.
 

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Question On AGC Design!!

Yes, I see your point.
But why OTA? Why not directly use 2 stage opamp(to repeat my earlier question)?

Giri
 

Anachip

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Re: Question On AGC Design!!

Hi Pixel and Giri,

I have gone through all your discussion on my posting about the AGC design and i managed to understand certain things and some are still unclear. From the discussion, i came to this conclusion, correct me if my wrong.

1) The comparator need to have a high open loop gain. For this i have read that it is better to have a 2 stage opamp for high gain contribution or a single stage opamp like folded cascode. From the schematic I posted, it sees to me that it is a single stage opamp which is M1-M5 and there is another stage M11-M12 which is forming integrator. So, if i were to design a two stage opamp, then the circuit will be M1-M5 followed by a common sourse amplifier. Then only i will cascade a integrator. Correct me at this part.

3) At the initial design, when Vpeak=Vrefm the output at Ro and Co need to be as such that the NMOS which is in paralled to resistor to be in off region. Meaning that, as Vpeak start to higher than Vref, it will start to turn on the NMOS, is this suppose to be??


4) Cf is actually performing the integrator job while Rf is there to provide output impedance?

5) Im actually to design this AGC for NRZ signal which will have bit 1 and bit 0 in random, then in this case how do i decide the value of Rf, Cf, Ro & Co, what criteria i need to know in order to set this values.

Hope i get some good feedback from you guys and thank you very much in the previous feedback.

Anachip:D
 

pixel

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Re: Question On AGC Design!!

Forget two stage.
Your gain is high enough with OTA amplifier. You dont need higher gain because it will make your loop unstable. OTA is good because it has rail-to-rail output.
Two stage amplifier has two poles , and dont like high capacitance at the output (leads to unstability), while AGC loop with OTA is more stable for higher output capacitance.

In this article is described your circuit.


M. A. T. Sanduleanu and P. Manteman, “A low noise, wide dynamic
range, tranimpedance amplifier with automatic gain control for
SDH/SONET (STM16/OC48) in a 30 GHz f BICMOS process,” in
Proc. Eur. Solid-State Circuits Conf., Sep. 2001, pp. 208–211.

In what range is your input current?
 

Anachip

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Re: Question On AGC Design!!

Hi Pixel,

I'm desigining my Transimpedance amplifier for the range of 5uApp to 2.5mApp in the 1.8V CMOS process with RGC differential configuration. That's why i need to understand the concept of AGC here. I have gone through the papers you suggested before while doing my research but not able to understand the circuit. ok, as you said, 1 stage OTA is already enough, then i for see that this 1 stage could give about 30 - 40db gain, which i guess will be fine. And this gain will be given by the transistor M1-M5. And what is the transistor M6-M9 for? Are they performing the current comparison and also the M11-M12 which u say is not a part of OTA as well. So, does this M11-M12 not included as a gain stage.

If I were to use a NMOS transistor as an input stage of building the OTA, does the M11-M12 still remain there as NMOS common source stage or in the other way around. Please explain me in this matter, as im confused and need to make myself clear before proceeding my design. Your feedback is really helping me.

Anachip
 

pixel

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Re: Question On AGC Design!!

M6-M9 are standard part of OTA amplifier
small signal:
im3 current is mirrored trough M7 then trough M6 to M8 (im8=im3 if all mosfets are equal, if not you current ratio would be proportional to their ratio)
im4 is mirrored to im9
Your output current is iout=im8-im9=gm1(Vpeak-Vref). This current is integrated trough m12, and lowpassed trough roCo to output.
Since integrator inverts signal you will have output proportional to -(Vpeak-Vref), and you should see how to connect your Nmos in order to have lower resitance(higher nmos Vgs) for higher Vpeak.

Anachip said:
Hi Pixel,
Your feedback is really helping me.
Anachip
Click helped me button, below my post : )

Added after 3 hours 11 minutes:

vgiri said:
To my understanding, Rf, Cf are for frequency compensation - correct me if I'm wrong. You need to ensure positive phase margin with these two.

Giri

This is not true!!! There is no Miller compensation if Rf is present!!!
m12 feedback makes that Cf is higher (Miller effect), but in the same time Rf is smaller for the same amount, and your output pole is RfCf.

Precisly: pole at the output of OTA is ro8||ro9||Rf/a *( Cf*a+Cgs12)=RfCf, where ro11,12 are mos outtput resistance (high), and a is m12 voltage gain.

->You can see that there is Miller effect only if Rf/a>>ro8||ro9

Poles summary:
1Output pole is w1= 1/RoCo - should be made as dominant
2OTApole w2=1/RfCf
3Non dominant OTA pole is w3=1/Cgs*gm4

To maintain stability w2>betaA0*w1
w3>>w2
where betaA is loop gain at small freq...
 

    Anachip

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