Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how do you use the virtuoso xl in your design?

Status
Not open for further replies.

nmtr

Member level 2
Joined
May 16, 2001
Messages
46
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Location
a Chinese university
Activity points
580
now i use virtuoso xl in analog custom ic layout,in my lab none use it before,please give some advise about it.thanks.
and please give me some advise about virtuoso custom placer and router too,
in my opinion it seems that custom placer and router are new version of ic_crfat(ICC), is it true?


<font size=-1>[ This Message was edited by: nmtr on 2002-03-22 16:47 ]</font>
 

Hi,

I use virtuoso to make custom Ic layout and to design the schematic in composer. With virtuoso we do DRC, extraction and LVS with diva routines.

Dracula can also be used for more powerfull checks or calibre, and see the errors in virtuoso.

If you have some more explicit questions, please do so.

Regards bastos
 

thank your kindly reply,but i just discuss is Virtuoso XL,which is different from Virutoso,blow is descirbe of cadence web

------------
Virtuoso®-XL Layout Editor is the next-generation, connectivity- and constraint-driven layout design environment. A task-oriented design approach provides direct access to automated placement, routing, verification and a robust set of interactive layout editing utilities. This new physical design solution maximizes custom layout productivity to deliver handcrafted quality layout in a fraction of the time of traditional methodologies.
-------------------------------------------
and in one of his success story of this product that say a new design flow have been used:
---------------------------------
The new design flow established for device-level place-and-route starts with the development of a Pcell library using ROD technology. VXL is then responsible for placing the transistors and the layout is routed by CCAR(cadence chip assebmly router). To ensure the application of correct rules by the whole team and a satisfactory routing result, a number of SKILL scripts were implemented by AMA and Cadence. For small standard cell applications VXL(virtuoso_XL) generates a layout view including connectivity. A few SKILL applications then generate a floorplan and VCP command files, which act as the starting point for VCP(virtuoso custom placer). The placed design is then transferred to CCAR for routing.
------------------------
i want to know 1) did the ic4.46 basic package inculde the VCP and CCAR?
2)more detain of each stage of the new design flow.like how to devolp the Pcell,
and its experiment.and so on.
 

Oh, Ok! I design only analog circuits that do not use P&R, so I could not help much in that.

Regards bastos
 

hi,friend
could you tell me how do you use hspice in cds? do you use it analog_artist? or dircetly in composer SE environment? if in analog_artist it seem that many useful sentence can't be use,if in SE environment,it seen the cds can't find the hspice view?in cds it only have hspiceS view,how do you solve this problm? or just use other methods? like using avanlink which dicribled in hspice's mauanl? thanks
 

you must create hspice view to use in artist for simulation

any have virtuoso xl tutorial?
 

do you means that i have to using skill language to devolpe my hspice view?it is too diffcult to do that,too many element too many sentence.
maybe a devolped package of hspice view exists like avanlink is a good choice.
cds don't contain VXL tutorial but it have many VXL manual,I have read it and fellow it introuduce,devolpe my tf,installed the sample Pcell.in this way i briefly master this tools,but if someone have some course material from Cadense,please share me a little.thanks
 

I will follow the original post:

Hi nmtr,

the generation of a complex pCell library matched to the composer symbols is needed. Then there is a automatic generation of the pCell layout from the schematics symbols. E.g. a MOS could have Width, Length, Number of Gate Stripes, Substrate Ties ..., all these generated components are then connected by rubberbands. Then could complete the connection process. I have taken a look on this tool. The problem is that a schematic is overspecified if it have to include parameters targeted for a specific layout configuration. Because did not know that in advance, e.g. if the schematic designer is a different one, you limit your layout flexibility. That is the drawback of that automisation.
 

hi,friend:
it seems that the sample Pcell in cds can be installed and specialed using your technogoy,as layer define,rule and so on,but when i use install program install pcell in my technogoy it will sucess firstly,but when i use it in layout,i will often find that many error occurs when cds execute the pcell skill program .i check those error,and find that it is some rules like the line wideth ,line space and so on are missed in pcell skill programs,so pcell can not execute ,
but in cds pcell install process,only part of that parameters which have to need by skill programs can be entried,some of importanct rules can not be entried in the install program at all,i have to examine the pcell skill programs and fill those parameter maualy ,when i finis this work,pcell will work well
but this flew is too terrible,too nervous.may i make a mistake in somewhere? i don't know and i often think that it is a bug of cds^_^
do you meet this problems?how do you solove this problems,thanks.
 

is pcell are the same for all fab?
 

nmtr said:
hi,friend
could you tell me how do you use hspice in cds? do you use it analog_artist? or dircetly in composer SE environment? if in analog_artist it seem that many useful sentence can't be use,if in SE environment,it seen the cds can't find the hspice view?in cds it only have hspiceS view,how do you solve this problm? or just use other methods? like using avanlink which dicribled in hspice's mauanl? thanks
You can just use hspiceS cellview to generate netlist in analog_artist
 

hi cyrabbit,

if a component has both hspice and spectre view, do I need to delete the spectre view, and place a hspice view. it's easy for one component, but for a large design, it could be a mess. is there any simple way to switch among those views.
 

nozone said:
hi cyrabbit,

if a component has both hspice and spectre view, do I need to delete the spectre view, and place a hspice view. it's easy for one component, but for a large design, it could be a mess. is there any simple way to switch among those views.
Why need to delete the spectre view?You have set netlist cellview and stop netlist cellview.
 

what is the difference of HspiceS, Spectre and SpectreS?
that is to say,
what is the advantagies of using HspiceS?
 

XL function is use cadence tool make schmatic
and director transfer to layout tool
so need the PDK (Process Design Kit)
PDK include the design and layout library
and Skill file ( for tool use )
so all job complete on cadence tool
 

zouwanghui said:
what is the difference of HspiceS, Spectre and SpectreS?
that is to say,
what is the advantagies of using HspiceS?

You have to use Hspice because you don't have device model in Spectre. The foundry supply the model in Hspice as default.
 

Who has used IC_C (IC Craftman) ? Is it easy ?
For a new technology, is it long to implement all constraint ?
For a new design ? For a new cell ?
Any comments are welcome.
 

I have used IC_Craftsman in the past. It's a pretty decent tool for routing analog cells...but if u need high speede layout it's not as good. It takes a long time to setup all the constraints...and it's much better manually
 

hi,friend
could you tell me how do you use hspice in cds? do you use it analog_artist? or dircetly in composer SE environment? if in analog_artist it seem that many useful sentence can't be use,if in SE environment,it seen the cds can't find the hspice view?in cds it only have hspiceS view,how do you solve this problm? or just use other methods? like using avanlink which dicribled in hspice's mauanl? thanks

To call Hspice in cds, you don't need the hspice view. All you need is to choode "hspiceS" as simulator and specify the model libraries. Then you can just follow the same procedures as you run Spectre in cds.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top