parasitics on board
For estimating pad capacitance you can just use the parallel-plate capacitor formula. Just add this into your simulation (toggle on and off) to see how much the circuit is affected. As frequencies go higher then this is more of a transmission line effect. To truly capture almost all the effects you must use microwave-design techniques where every component (with footprint) has well defined reference planes, and you know how it was measured. I'll plug Modelithics since they have a very nice CLR library with substrate dependant models and good reference planes at the footprints.
For instances where isolation is not a big concern you can just space metal at one substrate thickness away from transmission lines (when they are not too long) and not affect Z0 much. Now if coupling is an issue you can use EM simulation to get a feel on how closely you can space things. Don't need to simulate the whole structure, rather some test structures such as coupled lines. The Microwave Office EMEXTRACT feature is very handy for this as is Sonnet.
Using a thin PCB reduces coupling and via inductance, but increases pad capacitance. Choose a low Er material unless you need distributed elements in which case high Er will reduce size.