How do you normally handle metal fill generation in large matching arrays?

[RodrigoSP]

Hi everyone,

I would like to ask here how you normally deal with metal fill generation over large arrays.
Often, in smaller nodes, the matching array is big enough to require metal fill, but I have seen different approaches so far to handle it.

Up to now, the best in my opinion would be to manually generate metal fill shapes over the devices' active areas, in a regular way so all devices are covered with same amount of metal in all metal levels. But this requires a bit of manual work.
I am curious to know if somebody has any other ideas or suggestions for approaching this problem.


Thanks in advance

 

[timof]

Often, companies use scripts (provided by foundries or by EDA vendors, or developed internally) for automated metal fill generation.
This is much easier and faster than doing manual fill insertion - but, none of these scripts (to the best of my knowledge) take into account parasitics matching problem.

In other words - if you have a precision analog design, then automatically generated metal fill may introduce an asymmetry (mismatch) in parasitic capacitive coupling. That's why, for precision designs, layout engineers oftn opt for manual fill generation.