how do you make an open drain output on a 16v8 fpga?

[herwis]

Hi,
how do you make an open drain output on a 16v8 pld?
Thanks

 

[FvM]

It's available (only) in complex mode with input to the OE product term.

 

[herwis]

Thank u so much for ur reply, but the problem im new in this field, so could u give me more information and why it's available only in complex mode?

 

[FvM]

The question is answered by the 16V8 data sheet. For open drain output operation, you need individual control of OE terms of output pins. It's only available in complex mode. If you have a logic synthesis tool that supports GAL16V8, e.g Lattice ispLEVER, you can enter a behavioral description of your logic and try to make the tool compile it.