fpga_asic_designer
Junior Member level 3
Quick question. How do you guys handle async reset in your design.
Should I use the OPT1 coding below, or should I use the OPT2 coding below. If I use OPT1, then even if the iclk2 is not present, the flops with orst2 will still be reseted. If I use OPT2, then orst2 should have no recovery time issue, but if there is no iclk2, the orst2 will stuck high.
I.e.
input wire iclk1,
input wire iclk2,
input wire irst1, //in iclk1 domain. asynchronizally applied to flops
output wire orst2 //newly generated rst in iclk2 domain
//synchronization irst1 from iclk1 to iclk2
//counter in iclk2 domain to elongate the generated rst2
reg rst2; //generated signal
//mux for dft purpose
wire rst2_buf = (iSCAN_EN)?irst1
irst1 | rst2); //OPT1
wire rst2_buf = (iSCAN_EN)?irst1rst2); //OPT2
bufx12 A_BUF (.A(rst2_buf), .Z(orst2)) ;
Should I use the OPT1 coding below, or should I use the OPT2 coding below. If I use OPT1, then even if the iclk2 is not present, the flops with orst2 will still be reseted. If I use OPT2, then orst2 should have no recovery time issue, but if there is no iclk2, the orst2 will stuck high.
I.e.
input wire iclk1,
input wire iclk2,
input wire irst1, //in iclk1 domain. asynchronizally applied to flops
output wire orst2 //newly generated rst in iclk2 domain
//synchronization irst1 from iclk1 to iclk2
//counter in iclk2 domain to elongate the generated rst2
reg rst2; //generated signal
//mux for dft purpose
wire rst2_buf = (iSCAN_EN)?irst1
irst1 | rst2); //OPT1wire rst2_buf = (iSCAN_EN)?irst1
rst2); //OPT2bufx12 A_BUF (.A(rst2_buf), .Z(orst2)) ;