How do you get big amplification on an NMOS?

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Addez

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In school they teach us how to calculate on NMOS circuits, but we never learned the basics for how to design your own circuit.
I know how to give a bias voltage on the gate. This leads to a current on the drain, which leads to a voltage across the drain and source resistor.

But I never got guidelines on how to design a circuit.
I want BIG signal amplification and drain minimum power doing so.
What resistor should I change to increase amplification?
I'm guessing the drain resistor but I'm getting nonsense readings from LT-spice when I do that.

Please help me I'm getting nervous breakdown over this.
 

The transconductance of a Fet is fairy low. Like any transistor it can have a high voltage gain if its drain resistor is a current source instead and its load has a high impedance. The current source should produce the same DC current as a resistor.
 

How do I make the drain resistor a current source?
And by load resistance I believe you mean the load + drain and source resistors?
 

If you didn't learn about current source circuits then you can look in Google at some.

The load is the external load, probably capacitor-coupled. For high voltage gain you do not use a drain resistor, instead you use a current source that has a very high impedance. You might not need a source resistor unless it is a depletion mode Jfet.
 

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