#### kc295

##### Newbie

Example, assume we have a 64Hz baseband, so nyquist frequency is 128HZ, our modulator is capable from an SNR perspective of greater than 12 bits of resolution. Our OSR is 512X so sampling frequency is 64KHz. For simplicity sake assume a counter is our filter/decimator (aka accumulate and dump or sync filter) So we have a pcm bit stream loading into the “counter” at a 64KHz rate, we are clocking out at nyquist or 128Hz,(assume single stage decimation for simplicity) this means the counter will accumulate 512 bits per dump. The count can be anywhere from 0 to 511, and 512 bits can be decoded into a 9 bit word.

I've designed a couple of sigma delta modulators before, but my interest always ended at the pcm bit stream.

How do I get other than 9 bits out of this ADC?

I'm sure this is insanely stupid of me, but...............