How do you balance Generated clock?

[vikramc98406]

how to take care generated-clocks @ synthesis

How do you balance Generated clock with source/Master clock?

Any special inputs needed?

 

[vlsitechnology]

clock tree generated clock

I think balancing the clock is nothing but balancing the skew
and for that u need to check ur ctstch file
and control the skew to reduce the set up or hold violation
correct me if i am wrong
bye take care

 

[roger]

balance cts for generated clocks

While in the clk tree root, generate several clk signals in several delay step,
routing pre-delay clk to gated (or generated clk) signal

 

[xinsu]

generated clocks cts

I think your question is not clear,if you want balance all generated clk,you can define clock root pin if they generated from same source,and you can define clock groups if they come from different souces.if you just want to balance part of generated clock,you should generated cts in special paths

 

[chithrag]

hi please tell how to balance the skew between multiple clocks in a design in physical design

 

[xinsu]

Use clock groups as I said above

 

[sesl33]

You do a clock tree synthesis to balance the clocks.

 

[iwpia50s]

Your cts tool should be smart enough to know the parent of a generated clock and move the generating flop up the clock tree sufficient enough to balance the generated clock.

 

[vinayshivakumar]

In magma you can define skew groups , all other tools have similar config commands....

 

[Amruth]

balancing generated clock is nothing but balancing the skew

that what we r doing the Clock tree Synthesis

 

[raju3295]

i feel balanceing the clock means, have to balanece the latenecies, in IP we generally add a source latency to the clk pin equal to the diff of the latency values between the clock so that every clock latency becomes equal