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How do we synthesize analog HDL?

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rogger123

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analog HDL

hi
i have a doubt on hdls used to describe analog circuits.
as in the digital domain we have synthesis tools to generate the hardware for a given rtl code... how do we synthesize analog hdls?
is there any synthesis tool for analog ckts??
or are these hdls used only for simulation purpose??
 

Re: analog HDL

Indeed, AHDl are more used for fast simulation, higher level analog system level architecture exploration and generic circuit design.
 

analog HDL

synthesis tools for analog ckts?
Some fabs have this kind of tool for only special kind of circuits, such as memory...
 

Re: analog HDL

AHDL can create and use modules that describe the high-level behavior of components and systems. I only use it for simulation and replace it by a real circuit finally.
:)
 

analog HDL

I know there is a version of verilog used for analogue circuit modeling and design. It is as similar as the circuit description in digital verilog design. I am not sure what it is and very interested to know it in details.
 

Re: analog HDL

cawan said:
I know there is a version of verilog used for analogue circuit modeling and design. It is as similar as the circuit description in digital verilog design. I am not sure what it is and very interested to know it in details.

Hi,
infact there are two similar but different versions 8)

1) Verilog-A: used for analog modelling only
2) Verilog-AMS: used for analog-mixed signal modelling

go to https://www.accellera.org and download the LRM of Verilog-AMS to find out the details. also search the forum, u can find more info abt them.

thanks
sawaak
 

Re: analog HDL

Hi everyone,

I am in the university. And I am just wondering whether there are many guys in industry use the AHDL to do simulation. Thanks.
 

Re: analog HDL

i don't know how good is an analog cirtuit with describer language, but i prefer full-custom design

instead, can somebody with experience in that field, tell me how is the performance full-custom vs hdl description?
 

Re: analog HDL

full-custom design cannot be instead of AHDL. AHDL is mainly used for system level modeling and fast simulation. AHDL also have some special advantages. For example, We can build a PLL AHDL model in Phase domain.
:wink:
 

Re: analog HDL

There are analog devices that can be reconfigured like FPGAs. Lattice makes some devices with analog building blocks that can be changed to adjust gains thru R's and C's for example. Thus a multistage filter can be created with varying output response using blocks comprising of cascaded opamps.
 

Re: analog HDL

brain79 said:
i don't know how good is an analog cirtuit with describer language, but i prefer full-custom design

instead, can somebody with experience in that field, tell me how is the performance full-custom vs hdl description?

As far as I know, the high speed Digial cirucuit need full custome design instead of HDL-> synthesis flow. One good example is Intel's CPU. Using normal HDL-> synthesis flow, the CPU can not work at GHz.
 

Re: analog HDL

AHDL = analog HDL or Altera HDL ? Altera have HDL ..but
digital designer usually use Verilog/VHDL

as I know .. analog HDL have 2 type

1. Verilo-A
2. VHDL-AMS

and Antrism have a special tool can do "analog synthesis"
I never use it ... but some RD said it can synthesis some analog
circuit

maybe EDA vendor will design a "analog synthesis tool" in the future,
like "filter solution" can automatic synthesis Filter R/C value
and automatic synthesis OPA CKT ( usually OPA have
2_stage /cascode/foldcascode/ full-diff ... maybe can do a OPA
synthesis tool , and RD assign gain/bw/power .. EDA tool
can synthesis a simple OPA )
 

Re: analog HDL

Layout Analog HDL(LAHDL)
 

analog HDL

For analog circuits description best choice is Hspice and Verilog-a

For Mixed system description use VDHL-AMS language.
 

Re: analog HDL

You shold pay attention in CMOS Design
 

Re: analog HDL

Hi,

up to my knowledge the behavioral modeling in analog is mostly used to provide test vectors to your analog blocks to verify its functionality to a varied wide nature of inputs.

when it comes to full chip simulation with millions of MOS, thousands of BJT ,diodes, R ,L,C then it advised to replace few blocks with behavioral models to speed up the simulation else it will take several weeks to complete.

So mostly people will develop behavioral model along with the ckt level design and it will be validated against its device level counter parts so that they can be used at different levels of abstraction with out losing accuracy to an extent.

hope this helps!

thanks,
 

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