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As long as the frequency of one clock is an integer multiple of the other (3 * 50 = 150). The clocks can be made to be synchronous with fixed timing between the two clocks. Not sure about your first question. It is very general.
If the 50 MHz and the 150 MHz aren't derived from the same clock source (e.g. They come from two different oscillators external to the device), then they can not be considered synchronous as their frequencies and phase relationship will drift over time.
I consider a clock domain to be a single clock source that drives all clocked elements with that clock in a design. Even if there are two copies of 50 MHz that are synchronous to each other but drive different sections of logic, they are still two separate clock domains, albeit synchronous ones. In this case the two clock domains may have significantly different clock tree insertion delays.
I think my first definition is too limited. 100 MHz and 150 MHz can be made to be synchronous. One way is to derive them both from the same 300 MHz clock. Perhaps someone can provide a more expanded definition.
If they were both derived from the same clock source they could be considered synchronous, but because of the difference in frequencies every third rising edge of 100 MHz will line up with every second rising edge of 150 MHz, hence you will have extra clock edges that will reduce the setup time for transfers between the clock domains.
If they were both derived from the same clock source they could be considered synchronous, but because of the difference in frequencies every third rising edge of 100 MHz will line up with every second rising edge of 150 MHz, hence you will have extra clock edges that will reduce the setup time for transfers between the clock domains. View attachment 102943
Clocks with these kinds of relationships are used with suitable enable or control signals to select which edges are used in different paths in RTL designs. In other words, the edges which are not simultaneous are not used when going between the two clock domains. In the diagram, only the rising edges without arrows would be used between the two clocks. For example, a pipelined arithmetic function may use the three edges of the faster clock and only synch up the result with the every other edge of the slower clock. For example, I optimized an arithmetic divider by pipelining it in this way. This sort of technique may take a bit of hand crafting but can speed up overall processing times. As I recall, the tool I used (Quartus II) gave some support for these sort of multiple clock cycle paths in the timing analyzer.
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