Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How do these ESD protection circuits work ?

yoon

Newbie
Joined
Jul 28, 2021
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
7
There are two ESD protection circuits.
How do these two circuits work?
What is the difference?
Please let me know

clamp2.png


clamp1.png
 
Last edited by a moderator:
Solution
They are almost same..
First one uses the Capacitor between Bulk-Gate, second one uses an extra capacitor.
When ESD transient pulse appears, a current flows through the resistor and a voltage occurs between Gate-Source of NMOS transistors and this NMOS makes VDD-VSS short circuit in a temporary time slot.So protects the IC against ESD zapps.

BigBoss

Advanced Member level 5
Joined
Nov 17, 2001
Messages
5,112
Helped
1,528
Reputation
3,054
Reaction score
1,376
Trophy points
1,393
Location
Turkey
Activity points
30,742
They are almost same..
First one uses the Capacitor between Bulk-Gate, second one uses an extra capacitor.
When ESD transient pulse appears, a current flows through the resistor and a voltage occurs between Gate-Source of NMOS transistors and this NMOS makes VDD-VSS short circuit in a temporary time slot.So protects the IC against ESD zapps.
 
  • Like
Reactions: yoon

    yoon

    Points: 2
    Helpful Answer Positive Rating
Solution

yoon

Newbie
Joined
Jul 28, 2021
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
7
Thank you for answer.
and I have another question.
I'm wondering what's the difference between with and without inverter.
 

BigBoss

Advanced Member level 5
Joined
Nov 17, 2001
Messages
5,112
Helped
1,528
Reputation
3,054
Reaction score
1,376
Trophy points
1,393
Location
Turkey
Activity points
30,742
Thank you for answer.
and I have another question.
I'm wondering what's the difference between with and without inverter.
First circuit protects the IC against negative ( less than GND potential) spikes, second one protects both.
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
20,487
Helped
4,461
Reputation
8,931
Reaction score
4,490
Trophy points
1,393
Activity points
135,454
Hi,

I see VDD and VSS. But where is the input and the output?
What is the signal that should be protected aganst ESD?

Klaus
 

KlausST

Super Moderator
Staff member
Joined
Apr 17, 2014
Messages
20,487
Helped
4,461
Reputation
8,931
Reaction score
4,490
Trophy points
1,393
Activity points
135,454
Hi,

Makes sense.
And VDD is the signal that should be protected against ESD. Only power supply. No other signal is involved.

Although I think that supplies are not that problematic with ESD (external circuitry, big capacitors, fast capacitors, other load..) it surely is possible.

So it protects against overvoltage ... and reverse voltage.

Does anyone expect voltages higher than 10V (just as example) at VDD? with and wihtout protection..

I´m asking because ESD usually is in the range of kilovolts.

Klaus
 

LaTeX Commands Quick-Menu:

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top