How do I use Block RAM in my spartanII based design?

[Vonn]

I need to use a Block RAM in my spartan II based design ; this is the first time to use the logic core generator in the ISE5.1 .
I have followed all the steps in the core generator and it's completed successfuly , but after i added the created VHD file to my design I noticed that there is a sub file in the sources window called wrapped_filename ??
and when i tried to compile the generated ram file i have got an error message
"ERROR:HDLParsers:164 - C:/Fndtn/bin/divider/myram.vhd Line 111. parse error, unexpected $ "
Actually line 111 is the end of the generated code and there is no any $ ???
If any body had used the core generator before please give me a hand

 

[elektrom]

The alternative way is to use a pure VHDL code. XST could automatically instantiate BlockRAM directly from HDL code. No need to use CoreGen.

See chapter 2 of Xilinx Synthesis Technology (XST) User Guide.

-- Here is an example for single port BlockRam ---------
library IEEE;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_unsigned.all ;

entity sync_ram_singleport is
generic ( data_width : natural := 8 ;
addr_width : natural := 8);
port (
clk : in std_logic;
we : in std_logic ;
addr : in std_logic_vector(addr_width - 1 downto 0) ;
data_in : in std_logic_vector(data_width - 1 downto 0) ;
data_out : out std_logic_vector(data_width - 1 downto 0)
);
end sync_ram_singleport ;

architecture rtl of sync_ram_singleport is

type mem_type is array (2**addr_width-1 downto 0) of std_logic_vector(data_width - 1 downto 0);
signal mem : mem_type ;

signal addr_reg : std_logic_vector(addr_width - 1 downto 0);

begin

Singleport:
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
mem(conv_integer(addr)) <= data_in ;
end if ;
addr_reg <= addr ;
end if ;
end process singleport;

data_out <= mem(conv_integer(addr_reg)) ;

end rtl ;
-----------------------------------------------------------------------------

 

[Vonn]

Thank you , elektrom ...It works after i modified it to fit with my needs but i faced another problem that is..
i need to connect the data bus of the ram to the output world ( out of FPGA) to the common data bus . So i defined the data in the entity as inout ... but it didn't work ..I mean If you want to guide the synthizer to make it RAM , you MUST put din and dout and if you make it inout the synthizer would never put it as RAM .
If Am I wrong Plz correct my understanding

 

[elektrom]

XST is not so smart. you have to write code in its own style. The solution is cover is ram module by another module. Like this...

-----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY RAM512x16 IS
PORT(
CLK : IN std_logic;
ADDR : IN std_logic_vector ( 9 DOWNTO 0); -- Address
WE : IN std_logic; -- Write enable
OE : IN std_logic;
DATA : INOUT std_logic_vector (15 DOWNTO 0) -- Data input/output
);

END RAM512x16 ;

ARCHITECTURE RTL OF RAM512x16 IS

component sync_ram_singleport
generic ( data_width : natural := 8 ;
addr_width : natural := 8);
port (
clk : in std_logic;
we : in std_logic ;
addr : in std_logic_vector(addr_width - 1 downto 0) ;
data_in : in std_logic_vector(data_width - 1 downto 0) ;
data_out : out std_logic_vector(data_width - 1 downto 0)
);
end component;

signal DIN : std_logic_vector(15 downto 0);
signal DOUT : std_logic_vector(15 downto 0);

BEGIN

U1: sync_ram_singleport
generic map ( data_width=>9,
addr_width=>16)
port map (
clk =>CLK,
we =>WE,
addr =>ADDR,
data_in =>DIN,
data_out =>DOUT
);

-- Tristate buffer
DATA <= DOUT when OE = '1' else (others=>'Z');
DIN <= DATA;

END RTL;
-----------------------------------------------------------------------------

Good Luck!

 

[Al Farouk]

search LIB and XST xilinx documents they contains solution to your problems.

 

[dll_embed]

To use coregen, you no need to add in the vhd file. xst needs the .xco file.

You can invoke coregen from within ise by : new source=>core gen ip. Then the block ram will be automatically added in your project. It should work as expected.

 

[mehrara]

hi
when you want to use the ram component that you `ve generated with CoreGen you can find the component port definitiion in the vhd file that coregen has created. I have used Dual Port Ram from coregen several times and I had no problem.

 

[Vonn]

I've used the Core generator to have a single Block RAM ; The first lines in the VHDL file
contains an announcment :

-- You must compile the wrapper file ramcore.vhd when simulating
-- the core, ramcore. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "Coregen Users Guide".

ramcore : is the created vhd file and you can see the wrapper_ramcore as file in a sub window
" source in project " as a sub of the ramcore !!
I can't deal with this file ! It's marked by a red quesion mark
and when i click on it , the new window appears as you are creating new source ???
Also The created VHD file can't be compiled and gives the error :
ERROR:HDLParsers:164 - C:/Projects/MyProjects/RAM/ramcore.vhd Line 112. parse error, unexpected $
I have return back to the pdf "Coregen Users Guide" , but I couldn't find the solution for this problem
can any body give me a hand
Please make your post in a steps :
After I have got the vhd file created from the core gen. Knowing that Iam using ISE5.1
What should I do ?
1-
2-
3-

 

[mehrara]

hi
I created the same core(I mean single block memory) and after those commented lines ! it contains the following port definition:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY test IS
port (
addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
we: IN std_logic);
END test;

1. you should put the following code in your top level design:
compnent test
port (
addr: IN std_logic_VECTOR(7 downto 0);
clk: IN std_logic;
din: IN std_logic_VECTOR(15 downto 0);
dout: OUT std_logic_VECTOR(15 downto 0);
we: IN std_logic);
end component;
2. then instanciate the component and use it! thats all!!!