deepa1206
Junior Member level 3
simualte the netlist
Hi
I am learning about FPGA with Precision RTL from mentor. I was able to compile and synthesize the verilog code that i had written. I now want to test the functionality of the synthesized netlist which is also in Verilog.
What simulation tools can help me do this? I tried ModelSim , but it didnt work because the synthesized netlist has module instantiations such as OBUF , IBUF, FCDE, etc which ModelSIm does not recognize.
Can anyone help me with this one?
Thanks
Deepa
Hi
I am learning about FPGA with Precision RTL from mentor. I was able to compile and synthesize the verilog code that i had written. I now want to test the functionality of the synthesized netlist which is also in Verilog.
What simulation tools can help me do this? I tried ModelSim , but it didnt work because the synthesized netlist has module instantiations such as OBUF , IBUF, FCDE, etc which ModelSIm does not recognize.
Can anyone help me with this one?
Thanks
Deepa