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How do I simulate/verify a synthesized netlist?

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deepa1206

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simualte the netlist

Hi

I am learning about FPGA with Precision RTL from mentor. I was able to compile and synthesize the verilog code that i had written. I now want to test the functionality of the synthesized netlist which is also in Verilog.

What simulation tools can help me do this? I tried ModelSim , but it didnt work because the synthesized netlist has module instantiations such as OBUF , IBUF, FCDE, etc which ModelSIm does not recognize.

Can anyone help me with this one?

Thanks
Deepa
 

Hi,

Modelsim is one of the tools to simulate your design/netlist. However you need to add the vendor libraries/packages to the modelsim.ini file and maybe compile them before you can simulate your netlist.
The vendor libraries describe for example the OBUF, IBUF, etc.

You can figure out which vendor packages you need by looking into the generated netlist and looking for library/use clauses.

Devas
 
U would need to add compiled "unisim" libraries to simulate internal components of fpga. Install xilinx ise and run "compxlib" from command prompt.
 

it helped me. Thanks teja
 

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