kosen
Newbie level 1
infer ram with initial contents
hi ,all
I have a verilog code to do the ST image process.
There are 800 ,4bit data reg for one color ,ex:reg signed [4:0] eramB[799:0]
Final I will creat three reg , but it will Synthesis fail because over the Slices and LUTs.
So I want to replace the REG to BRAM.
In fact, I also use the ISE to gen the BRAM(RAMB16_S18) code.But I don't how to instead it in my code and how could I know it work corret? @@
below is the my simple verilog about the reg and declare, the last is the ISE gen code .
------------------------------------------------------
module threshold ( Ycon,//y-aixs
Xcon, //x-axis
rin, //R
//---output
rout,
);
input [7:0] Rin;
input [10:0] ucon;
input [8:0] decon;
//--------------OUTPUT
output [3:0] rout ;
reg [3:0] rout ;
reg signed [9:0] rth;
//------------integer
integer i;
reg signed [4:0] eramB[799:0];
//------------error reg
reg signed[4:0] k;
wire [9:0] er1temp = (decon>1) ? (eramB[0]*5 + eramB[1]*1 ) :0 ;
wire [9:0] er3temp = (decon>1) ? (eramB[ucon-1]*3+ eramB[ucon]*5 + eramB[ucon+1]*1) : 0 ;
wire [9:0] er5temp = (decon>1) ? (eramB[798]*3 + eramB[799]*5 ) :0 ;
wire [9:0] er7temp = k*7 ;
....
....
.....
endmodule
RAMB16_S18 #(
.INIT(18'h00000), // Value of output RAM registers at startup
.SRVAL(18'h000000), // Ouput value upon SSR assertion
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
// The following INIT_xx declarations specify the initial contents of the RAM
// Address 0 to 255
.INIT_00(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
.INIT_01(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
...
) RAMB16_S18_inst (
.DO(DO), // 16-bit Data Output
.DOP(DOP), // 2-bit parity Output
.ADDR(ADDR), // 10-bit Address Input
.CLK(CLK), // Clock
.DI(DI), // 16-bit Data Input
.DIP(DIP), // 2-bit parity Input
.EN(EN), // RAM Enable Input
.SSR(SSR), // Synchronous Set/Reset Input
.WE(WE) // Write Enable Input
);
hi ,all
I have a verilog code to do the ST image process.
There are 800 ,4bit data reg for one color ,ex:reg signed [4:0] eramB[799:0]
Final I will creat three reg , but it will Synthesis fail because over the Slices and LUTs.
So I want to replace the REG to BRAM.
In fact, I also use the ISE to gen the BRAM(RAMB16_S18) code.But I don't how to instead it in my code and how could I know it work corret? @@
below is the my simple verilog about the reg and declare, the last is the ISE gen code .
------------------------------------------------------
module threshold ( Ycon,//y-aixs
Xcon, //x-axis
rin, //R
//---output
rout,
);
input [7:0] Rin;
input [10:0] ucon;
input [8:0] decon;
//--------------OUTPUT
output [3:0] rout ;
reg [3:0] rout ;
reg signed [9:0] rth;
//------------integer
integer i;
reg signed [4:0] eramB[799:0];
//------------error reg
reg signed[4:0] k;
wire [9:0] er1temp = (decon>1) ? (eramB[0]*5 + eramB[1]*1 ) :0 ;
wire [9:0] er3temp = (decon>1) ? (eramB[ucon-1]*3+ eramB[ucon]*5 + eramB[ucon+1]*1) : 0 ;
wire [9:0] er5temp = (decon>1) ? (eramB[798]*3 + eramB[799]*5 ) :0 ;
wire [9:0] er7temp = k*7 ;
....
....
.....
endmodule
RAMB16_S18 #(
.INIT(18'h00000), // Value of output RAM registers at startup
.SRVAL(18'h000000), // Ouput value upon SSR assertion
.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE
// The following INIT_xx declarations specify the initial contents of the RAM
// Address 0 to 255
.INIT_00(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
.INIT_01(256'h0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000),
...
) RAMB16_S18_inst (
.DO(DO), // 16-bit Data Output
.DOP(DOP), // 2-bit parity Output
.ADDR(ADDR), // 10-bit Address Input
.CLK(CLK), // Clock
.DI(DI), // 16-bit Data Input
.DIP(DIP), // 2-bit parity Input
.EN(EN), // RAM Enable Input
.SSR(SSR), // Synchronous Set/Reset Input
.WE(WE) // Write Enable Input
);
