How do I generate a 50Mhz clock on Altera Stratix II

[y7wu]

stratix ii high frequency sine

Hi there,

We're trying to generate a 50Mhz square wave clock on the Altera Stratix II to send to an off-board chip.

The way we're doing this right now is using the on board 100Mhz crystal oscillator and implementing using the following VHDL block. where in_clk is the 100Mhz crystal oscillator and wave_clk is the output (supposedly 50Mhz square wave)

architecture square_wave of square_wave_test is
signal wave_clk : std_logic;
signal count : unsigned ( 2 downto 0);
begin
process(in_clk)
begin
if rising_edge(in_clk) then
wave_clk <= not wave_clk;
end if;
end process;

process(wave_clk)
begin
if wave_clk = '1' then
out_pin_array <= "11111111111111";
else
out_pin_array <= "00000000000000";
end if;
end process;
end square_wave;

The problem is that we're getting a waveform thats not like a square wave at all. (see attached image).

We suspect the 100Mhz oscillator (which is a sine wave) is unable to replicate the higher frequency component of a square wave.

It could also be our probe, but the bandwidth of our probe is 500Mhz (Agilent 10073C) see
http://www.home.agilent.com/agilent/product.jspx?nid=-536902770.536879135.00&cc=US&lc=eng

so we're ruling out the probe as potential issue.

How would you generate a 50Mhz square wave clock? Is it better if we use the PLL, but wouldnt that generate sinewaves as well? How do I know if the output pin can be switched at such high frequency?

Thank you.

 

[FvM]

altera fpga pin current strength

To answer your original question, I can say, that your code generates a 50 MHz square wave at the output. The signal wouldn't be basically different when using a PLL with a dedicated clock output. The deviations visible in the screenshot are related to FPGA external circuit and probe behaviour rather than synthesized logic.

A few points are unclear from your post: What's the oscilloscope bandwith? What's the external trace and (possibly cable) length connected the FPGA output pin? If external trace or cable is present, where is the probe connected? Which IO-standard and current strength are selected for output? Did you use the 10073C ground bayonet or standard ground lead?

I would doubt in general, that a 50 MHz clock could be exactly reproduced with a passive high impedance probe, but it should look better as shown. This could be due to additional load (probe already implies 12 pF) at the pin and inappropriate probe ground connection. You should always use the ground bayonet for a undisturbed fast signal measurement.

As a special point, the signal unsymmetry needs an explanation. I think, it could be due to unterminated trace or cable load in conjunction with slightly unsymmetrical output drive strength. I can't decide if the ripple is from line reflections or ringing caused by probe ground lead. Also other circuit could be connected to the pin.

 

[y7wu]

The oscilloscope bandwidth is 500Mhz, (Agilent MSO6054A with 4GS/s). There is no external trace, i.e the probe is directly connected to the output pin of the board.
the probe cable length is 1.5m

IO-standard is 3.3V (LVTTL), current strength is unknown (is this something I can assign in software?)

I was using the standard ground lead and I used the ground bayonet and got better results. Please take a look at the new uploaded image.

If as you mentioned that 50Mhz clock cannot be reproduced exactly with high impedance passive probe. What kind of probe should I use? I am going to be analyzing a lot of high speed digital signal. should I buy the oscilloscope logic probe (i.e Agilent probe 54620-68701). What kind of probe would you recommend to get a good signal?

Thank you so much. How can I give you credit for helping (i.e increase your help count)

Added after 1 minutes:

The new capture with ground bayonet

 

[FvM]

Hello,

we're getting closer to the problem. 6054A should be fast generally fast enough to display the said signal, also the passive probe with the ground bayonet should give results of sufficiant accuracy in most cases. Now, as you're effectively increasing probe bandwidth by removing the lead inductance, you can see more details of the signal. Now, you can almost "see" the origin of the deviations from squarewave. There is actually a smaller 1ns width positive pulse superimposing both signal signal edges. This pulse is most likely due to simulaneous switching noise (SSO) or to use an older term ground bounce. Just try to disable the other outputs from your out_pin_array except for the probed one and watch the difference.

The cause is the current flow in ground pins during output switching, increasing with the number of switched outputs. The effect could cause complete failure of a design in some cases. To some extent, it depends also on PCB properties and package dimensions. With Stratix II, it should be basically limited due to BGA package with a lot of ground pins.

Current-strength settings, available in pin-planner or assignment editor also affects SSO respectively ground bounce. The setting defaults to maximum, but should be reduced to lower value for most FPGA outputs to my opinion. This effectively is identical to setting a series termination for an output pin, both options are utilizing a number of parallel transistors at each output. You should also try the effect on output waveform. As a particular point, lower current strength could help to achieve a better signal quality for the intended off-board connection.

My favourite probe would be a 1156A active probe, or a lower-priced third party product. Also a 500 ohms resistive probe gives good signal quality with low impedance outputs.

Finally, I don't chase points. I think the option is somewhere in profile tab.

Regards,
Frank

 

[echo47]

How do I generate a 50Mhz clock on @ltera Stratix II

Approximately how long is the PCB trace between the FPGA pin and the output connector? You could be seeing some signal reflection interacting with the FPGA's output impedance.

As FvM suggested, a resistive probe works very well due to its low input capacitance. It has a rather low input resistance, but that's ok in many digital circuits. Here's a good home-made version:
https://www.emcesd.com/1ghzprob.htm

A nice FET probe or differential probe is very handy too, but they are rather expensive.

 

[y7wu]

Hi there,

I turned off the other outputs and indeed the waveform improved! I really must thank you for walking me through the debugging process. I believe I have a usable square wave.

To answer your question echo47, the FPGA and the output connector are separated by about 2 inches.

I'm looking to purchase some probes. the 1156A is rather expensive, but I will ask if we can get one around here. Do you have any lower price alternative off the top of your head?

Thanks for suggesting resistive probes. I will look them up as well.

Thank you guys very much!
(btw I've attached the waveform I captured with other outputs disabled)

 

[FvM]

Remaining signal distortion may be due to probe effects. That's why I said, it may probably not be exactly reproduced with a passive high impedance probe. A homemade resistive probe as suggested could be a simple option. Having an oscilloscope with 50 ohms input, you would of course ommit the 50 ohms load from the directions, reducing the resistive probe to a 50 ohms coax cable with a small ≈450 or ≈950 ohms resistor at one end and a BNC connector at the other. 500 to 1 GHz FET probes are available from different manufacturers, also used Tektronix or HP FET probes are for sail at Ebay and electronic surplus.

 

[muralicrl]

Hi Friend,

Your VHDL code for division is very much correct. But in your design what you have to ensure is, since you are dealing with high frequencies like 50M and 100M they have to be dealt with the FPGA throuhg dedicated clock in and clock outputs only.
Please ensure this and check for this. I experienced same many times.

OK, if you need more details don't hesitate to contact me.

Regards,
N.Muralidhara
MSRS, CRL-Bg

 

[FvM]

I would clearly contradict a necessity of using a dedicated clock output here. As only advantage, the delay of an dedicated clock output is exposed to somewhat smaller variations. So if a design has a very tight timing closure related to outputs, this could be meaningful. In case of a PLL clock, you may want to increase hold time of data outputs related to a clock output, which could be another reason to use a dedicated clock output.

The observed signal deviations aren't related to possible selection of dedicated clock output at all.

 

[muralicrl]

Hi,

Send the derived clock through a dedicated clock out pin of the FPGA.

In case you need more detail, don't hesitate to contact me.

regards,

N.Muralidhara
MSRS, CRL-BEL