AlexKeys
Newbie level 2
Hello,
I have synthesised my Verilog HDL code in Synopsys DC and now I have to do a timing simulation. I do not want to use Xilinx or Altera tools as these will give me FPGA results. I want to know how to do the simulation taking into consideration my technology libraries (I suppose there has to be some resemblance of the tech files I used for synthesis) and netlist. I will be grateful for anyhelp offered. Thank you in advance.
I have synthesised my Verilog HDL code in Synopsys DC and now I have to do a timing simulation. I do not want to use Xilinx or Altera tools as these will give me FPGA results. I want to know how to do the simulation taking into consideration my technology libraries (I suppose there has to be some resemblance of the tech files I used for synthesis) and netlist. I will be grateful for anyhelp offered. Thank you in advance.