How do I asynchronously launch a clock pulse for four counts, then stop

[SLIman]

I'm trying to build a digital filter. I want to kick off an output pulse that runs for just four cycles that is 1.5ms high, 1.36ms low 4 times, then stops and waits for the another valid trigger input to start it all over again. However, After the initial "good" rising edge there is about 10.3ms of noisy "false" edges I want to ignore, then the trigger input gets quiet (low) for about 14.5ms which is follow by another "good" rising edge trigger (process repeats).

I want to ignore those false edges. I don't want multiple starts. Perhaps a one-shot counter?

Thanks

 

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If you are having a bunch of false triggers you should add a debounce circuit to the trigger input. I'm assuming this trigger is coming from something like a switch.

There is a debounce circuit for both VHDL/Verilog here: https://eewiki.net/display/LOGIC/Home

 

[SLIman]

If you are having a bunch of false triggers you should add a debounce circuit to the trigger input. I'm assuming this trigger is coming from something like a switch.

There is a debounce circuit for both VHDL/Verilog here: https://eewiki.net/display/LOGIC/Home

No, this is a noisy LVDS transmission line. There is an external LVDS to TTL converter that does a pretty decent job of passing "everything" through. I don't have control over this board as it is in production. I have added a schmitt trigger to the input side of my CPLD which cleans things up "somewhat", but not good enough. I have the pulse train regenerated in VHDL, but not sure how to consistently kick it off. Perhaps some sort of non-triggerable one shot. I'm interested in ideas and the VHDL for anyone who has done something like this.

Thanks

 

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What kind of waveform is this LVDS transmission line producing? and what ideally should it be producing?

If it's not a debounce issue how about (for lack of a better term) a post-edge-debounce circuit.
I think you'll have to do some "digital filtering" based on the duration of the incoming pulse, basically ignoring any edges following your initial edge until it's longer than a certain duration. You can take inspiration from the link I posted in #2 and enable the counter and the compare after you've detected an edge and ignore any pulses during this filtering time.

I think you should really get a handle on why your LVDS transmission line is so bad (is this over some cable?). What you are doing here is a band aid for something inherently wrong somewhere else. The whole point of using something like LVDS is it's differential and should theoretically reject common mode noise up to a certain point. Almost seems like the impedance isn't properly matched and your getting horrible signal integrity or if it's over a cable you're using an unshielded cable that runs next to something that is generating a large amount of noise.


Regards

 

[SLIman]

The LVDS signal is not data, only timed pulses for a camera high power light source (IR). The noise is probably due to a number of factors on a different board (not mine that interfaces with it). Nevertheless, I must clean it up as best as I can. The design works pretty good even with the noisy pulses, I just don't like the heat it generates on my FET drivers as they are constantly pulsed unnecessarily. Thanks, I'll check out the link in post #2.

 

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The LVDS signal is not data, only timed pulses for a camera high power light source (IR). The noise is probably due to a number of factors on a different board (not mine that interfaces with it). Nevertheless, I must clean it up as best as I can. The design works pretty good even with the noisy pulses, I just don't like the heat it generates on my FET drivers as they are constantly pulsed unnecessarily. Thanks, I'll check out the link in post #2.

Good luck with that, looks to me like the other board design has problems that should be fixed.

I understood you weren't sending data over the LVDS, but signal integrity is more than just sending data it's the quality of the received signal after going through transmission lines and connectors before it arrives at the receiver. In your case the other board or the interconnection between boards is causing transmission line issues. Do you have a TDR you can use to check the connection between the transmitter and receiver and check to determine if you have any severe discontinuities?

If the problem has more to do with the power on that other board, then they probably should have isolated the LVDS supply from all the noise with an LDO.

Regards

 

[BradtheRad]

I want to ignore those false edges. I don't want multiple starts. Perhaps a one-shot counter?

Thanks

The 4017 decade counter is handy if you want to count 4 cycles, then the fifth output pin changes state.

You can reset it by connecting the sixth output pin, through an inverter, to the Enable pin.