How do i achieve 100% Code coverage ?

[raghavathej]

Hi,

Is it possible to achieve 100% code coverage for complex design ?
(code is about 1000 lines with many always and if-else statements)
Is it necessary to achieve 100%?

Reaching coverage results from 0 to 80% may take few hours.
But it takes days to reach from 80 to 85%.
Also, if i don't code "else" part of if-else statement, then unless i give "else"
i cannot cover full statement, but i don't need "else" statement at all.
First of all why should i be modifying my RTL code for code coverage, instead
i should be giving more stimulus.But i am forced to include "else" statement or
my coverage is not increasing and many such problems .
What do i do?. How do i cover false part of "else". What different should i do ?

Thanks A Lot,
Awaiting your responses,
Raghava

 

[snishanth512]

What kind of ASIC are you using ???

Clock timings ???

 

[raghavathej]

I am using Cadence tools. NCVerilog

Cadence ICCr Tool which reads the code coverage.

Code is basically a interface between 2 protocols, coding in verilog.

 

[rca]

At least, in our design center all lines must be cover, or explained why it could not be covered.
The statement coverage is not mandatory, but we look at to know if some code are fare to be covered.

 

[amitjagtap]

As per my knowledge all code coverage is not necessary.... But you should have all Branch coverage...including ELSE part is situation dependent....Normally all code coverage tools follow some algorithm, some fixed way of testing code...its not application or situation dependent...So finally you should analyse and able to decide, justify what thing is required and what not.