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How do DRC violations occur even if we give lef files as design rules?

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biju4u90

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In digital physical design, how do DRC violations occur even if we give lef files as design rules? In other words, why do the geometry violations like minimum spacing violations occur even though the minimum spacing requirements of metal layers are specified in the lef file?
 

On which technology you are working.If you are working on lower nodes it is because in place and route it is placing the metals irrespective of the metals beside so as it cannot maintain minimum spacing it is giving errors which is what i feel.
 
Sometimes because the router can't work out how to do it without creating a violation, because congestion is too high.
 
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