How close can I place the pads ?

[ASIC]

Wirebonder clearance

I am working on an IC with a LOT of I/O. How close can I place the pads and be sure that the wire-bonder doesn't hit already bonded wires? I.e. distance in microns from pad-centre to neighbouring pad-centre.



ASIC

 

[cdic]

actually you need to do the package analysis for your design, in general it's done by fab vendor. what you need to do it's just place IO pads to make sure it will not violate the DRC rule, and then send you pad location map to the vendor.
as the matter in fact, you should provide it during the floorplan stage, or it's painful in the later stage if you have to modify it.

Regards
cdic

 

[ASIC]

The fab standard cells has a pad centre to centre distance of 110 micron, and it doesn't violate any DRC rule. My worry is that it will give problems during bonding.


ASIC

 

[cdic]

yeah, sometimes it maybe has some problem. so you need to do the package analysis to make sure whether it's bondable or not. and in general it's done by fab.

cdic

 

[ASIC]

Thanks cdic, As we package one place and fab somewhere else, I will check with the packaging house.


ASIC

 

[rfsystem]

You can use tigther spacing e.g 70-80um if you haver tighter control of the bonding angle and use staggered pads. That mean that you have even and odd pad rows with about 120-150um different spacing to chirp border or scribe lane. Further staggering does not increase density. The main reason why you could do that is that is the difference between bondwire thickness and bondbump is about 2..3.

 

[rfsystem]

You can use tigther spacing e.g 70-80um if you haver tighter control of the bonding angle and use staggered pads. That mean that you have even and odd pad rows with about 120-150um different spacing to chirp border or scribe lane. Further staggering does not increase density. The main reason why you could do that is that is the difference between bondwire thickness and bondbump is about 2..3.

 

[Nobody]

It can be verified by bonding simulation. I have heard one company steal(violate) FAB's design rule and leave only 10 um between the bond pad's edge.

 

[ASIC]

To all that have replied, thank you.

1) rfsystem. I was actually thinking of staggering the pads, but didn't know if it was feasible. Now I know

2) Nobody. As I have the drawing of the lead-frame from the packaging house, is there some way of doing the bonding simulation myself, or does it requre more than "drawing a few lines on a piece of paper"? Any software required for this?


ASIC

 

[Nobody]

It need some data from package manufactor to input .
One of my friend do the job in design service company.
They use 'Sabond' . All chips should pass the bonding simulation b4 tape-out in their company's flow. It test for the electric parameter and mechanic parameter .