How clock gating affects the critical path of a design?

[vivek_p]

I want to know whether clock gating will affect the critical path of the design? Will Clock Gating change the critical path of the design

Before clock gating , critical path delay was 10 ns
After clock gating, critical path delay is 6 ns (And that too in another path !!!)

How can this happen. Can anyone explain.

 

[shelby]

Clock gating

It can add clock skew if you dont balance your endpoints. What stage of the design are you at?

 

[vivek_p]

Re: Clock gating

But how can it decrease the critical path delay

 

[AdvaRes]

Re: Clock gating

Hi,
Clock gating does affect critical path depending on clocking. Actually, clock gating results in a small delay Δ to the gated clock. If this same signal will be used to clock two DFFs of a synchronous structure, the critical path remain the same.
However if you will use The original clock to synch the first DFF and the gated clock to synch the second DFF the critical path increases or decreases by the amount of the delay due to the gating.

 

[GrandAlf]

Clock gating

Perhaps the gating you are using is higher current drive and thus charging the track capacitance quicker whilst the original clock could be now driving a lower capacitace load. Just a thought, maybe completely wrong!