How Clk timming affects a design in FPGA?

[xtcx]

fpga proces clk

Hi Friends!, I'm doing a QPSK communication project.And Using Virtex-4,Xilinx ISE8.2i. My ADCs and DACs require 100 MHZ as clk input in order to work. In our circuit,we have not provided a separate crystal or oscillator for adc\dac in PCB. So While programming, I use to assign the clk pins of dac\adc to one of the FPGA input pin. And in coding,I will force the FPGA system clock of 100MHZ to the adc\dac pin through FPGA. Now the issue is, my design timming has achived only 43MHZ(as Shown in Synthesis Report).So Will this make any problem in driving 100MHZ clk to adc\dac?. will the FPGA give 100MHZ or 43MHZ ?...How will my FPGA provide 100MHZ to adc\dac while my design's maximum timming is 43MHZ only? .Please help me out. I can't proceed any further...Thanks in advance friends!.....

Eg. Coding...,
{
Entity
{
}
Architecture ......
...
.
.
Begin
ADC_CLK <= Sys_clk; -- assigning 100Mhz to adc
DAC_CLK <= Sys_clk; -- assigning 100Mhz to dac
Process(clk)
begin
....
.
.
...
End Process;