Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

how check loading effect in adc

Status
Not open for further replies.
J

jagrut

Newbie level 3
Joined
Aug 26, 2011
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,298
sir
i have design cmos flash adc. for that i generate vref using nmos but when i give that to comparator the voltage is change. how can i remove this error
 

Does the comparator present a resistive load to vref? Show your schematic!
 

erikl said:
Does the comparator present a resistive load to vref? Show your schematic!
Click to expand...

sir i want to connect my J1 with In J1 is of 1.68 volt which i want to give In ..i am sending image of my schmetic
**broken link removed****broken link removed**
 

jagrut said:
**broken link removed****broken link removed**
Click to expand...

Sorry, currently can't read your attachments (by clicking them, they respond: "invalid attachment").

Better insert such schematic pictures via the "Insert Image" icon in your reply menu.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top