How can you mix two data lines and send it by a serial line?

[7rots51]

mix two data lines?!

hello
If you have 2 serial data lines with manchester encoding at 28kbps,how can I mix them and send it by one serial data line at upper speed like as 56kbps ?
(At receive end ,I want to seperate it again and have the original 2 data lines)
Please help on this.

 

[mr_ghz]

If you want to multiplex two serial lines to one, it's not enough that your
'output' line has twice the datarate than the inputlines. The reason is
that you need a sync-signal.
One easy way is that you synchronize the two input-channels (they
need to have exactly the same bitrate or you will get bitslips). This can
be done with two D-flipflops.
After that you set up a outputchannel with 3 times the input datarate.
This channel transmits first a logic '1', second the state of inputline '1',
third the state of inputline '2' and so on. The signal could also be
manchester-coded.
The receiver divides the inputsignal in three paths. The first path has
to be a '1' in every case. If it's not, it has to shift it by one bit. So you
have designed a simple synchronisation.
The complete stuff (RX and TX) can be implemented in a small CPLD like
a 3064 from Altera.

Greets

 

[7rots51]

The that is given by mr_ghz have a problem if the synchronization is lost in the receive end ,by which method it can sync it?
In other way ,how we can seperate two line data?
I think the above method is not reliable ,I think sending data in packets (contain several bytes )with sync and CRC bytes is more reliable but I am looking for a more simple and lower kbps way!
please think on this topic and give comments!

Regards

 

[flatulent]

FDM

You can also use frequency division multiplexing. Amplitude modulate a higher carrier with one of them. At the receiving end filter them apart and emvilope detect the AM portion.

To be practical, the RF carrier can be from any clock oscillator available in the circuit and the modulator is an AND gate. If the carrier frequency is different enough from the baseband data rate, simple RC filters can do the separation of the signals. The demodulator is just a diode to a parallel RC network. The time constanat is about the duration of one or two carrier cycles.

 

[mr_ghz]

Hi 7rots51,

if you loose the sync while receiving, you will resiync after a while:
Every 1st bit (of three) must be a logic '1'. If it's not you skip one bit and
check the next. It can take a while until you find the correct sync, but
if you are transmitting the chance is very little that (over a longer period
of time) another channel is taken as sync.
Sure it's better to send data in packets with CRC and so on, but it's much
more complicated and you have to use a microcontroller.

Greets

 

[7rots51]

to flatulent:
the data rate can be up to 64kbps for each data line ! and the data is transmitted on a cable that is long ! I think the cable BW is limited and I can not use modulate them on a cable at two different carrier frequency.
!

to mr_ghz:

there are some situation that the sync is not possible or data of two channel will be swaped in receiver end.

data line 1: 111111111111111
data line 2: 000000000000000
mixed: 110110110110110110110110110110110

the receiver can get:

for line 1: 000000000000000
for line 2: 111111111111111

the receiver never get right data!!!!

bye

 

[mr_ghz]

hi 7rots51,

This is true, but can be solved easy: If you pass every of both data-
streems through a self-synchronizing scrambler (a thing you should
always do before transmission, to remove dc-components) this problem
will never occur, and sync will function correctly.
This kind of synchronisation is often used in telecom-applications (but
for more channels).

Bye

 

[7rots51]

hi mr_ghz

do you know a IC that can do this task?

how can I remove dc ?I think if I use encoders like as manchester then the speed (kbps) doubles and I have bandwidth limitation in my application.
is there a way to remove dc and such problems without doubling data rate?

you said: "If you pass every of both data-streems through a self-synchronizing scrambler" please specify the methods and give me some links and helps on this.

best regards
7rots51

 

[mr_ghz]

Hi 7rots51,

I think it would be best if you implement your 2-to-1 multiplexer together
with the two scramblers in a CPLD. It's possible to do the scrambling with
a TTL-shiftregister and EXOR-gates, but the other stuff must also be done.

In the attachement you find a schematic of such a scrambler. It works
similar to a 'standard' PN-generator built of an 8-Bit shiftregister with an
EXOR at bit0 and bit2. A little bit special is the connection to the input
data, but see yourself.

Bye

 

[silvio]

Hi 7rots51,

The manchester encoding technique it's by far the best solution to remove DC components.
Even if you'll use only one channel, the bandwidth doubles, since for each byte you must send two.
For 0 you must send 01.
For 1 you must send 10.

On manchester encoder technique it's easy to recover if you loose the synch while receiving since you have signal transitions for each of 1 or 0 in the stream.
Thus you can quickly resynch.

mr_ghz wrote:
After that you set up a outputchannel with 3 times the input datarate.
This channel transmits first a logic '1', second the state of inputline '1',
third the state of inputline '2' and so on. The signal could also be
manchester-coded.
The receiver divides the inputsignal in three paths. The first path has
to be a '1' in every case. If it's not, it has to shift it by one bit. So you
have designed a simple synchronisation

This is a simple and good solution for two ordinary stream of data. But definitely not for manchester encoding.
Why? It's fairly simple. If one of the sources stops transmision, whatever the reason, when the receiver divides the input signal in three parts.... Well, guess what's the data belonging to the path of the second source.
In manchester encoding a 0x00 bytes it's sent as two bytes 0x55 followed by 0x55. There will be no doubt for the receiver that the source wants to transmit 0x00 and nothing else.
Look at mr_ghz two D-flipflops behaviour, required for synch and tell me how receiver will feel the difference between 0x00 and 0 as idle line (when one of the source finished his stream).


7rots51, you ask for a special chip suitable to do the job. If you have access to a programmer device for Ubicom SX microcontroller I can provide the hex file for both receiver and sender.
Otherwise, I can try to rewrote the code for MCS51 series, but since it's based on bit bang routine there will be not too much to do on main loop.
You'll loose the timer 0 as well. But SX it's much suitable for this due to the known latency interrupt as jitter free 3-cycle internal interrupt response.

One more question: it's your serial stream of data bordered by stop and start bits like in RS232 communication, or it's a contiguos stream of bytes ?

Regards,
Silvio

 

[mr_ghz]

Hi silvio,

the idea was to manchester-encode the output-datastream after combining
the two channels.

Bye

 

[7rots51]

hi
to mr_ghz:
If after combining to channels we do manchester encoding ,then at receive end we have the same problem in above post:

data line 1: 111111111111111
data line 2: 000000000000000
mixed: 110110110110110110110110110110110


doing manchester encode

send stream

receive stream

decode manchester code

seperate two data streams,the receiver can get:

for line 1: 000000000000000
for line 2: 111111111111111

a false receive!

I need more info on data scrambler and a better method if you know.



to silvio:
I have continuous stream of data from two channels.

I like to know general techniques used in telecomm for mixing several channels ,where can I find some info?

Can you provide for me the algorithm of program that you write for SX micros? I can write the program for cygnal 8051 with that algorithm.



Regards

 

[mr_ghz]

Hi 7rots51

Do you have an idea how you would implement it? If you plan to use a
CPLD (Altera) I can create you a schematic.

Bye

 

[7rots51]

Hi mr_ghz
The CPLD idea is very good for this task.If you post the sch it will be a great help for me.
Please if you know more links on this ,post it.

I also need some information on manchester encode and decode sch and theory.

bye

 

[silvio]

Hi 7rots51,

I'll provide the code for you, but please allow me few days to change a little for additional second channel that is missing now from my implementation.

You can read something about harware implementation in CPLD:
Manchester Encoder - Decoder targeted to the Xilinx XCR3064XL-7VQ100C CoolRunner CPLD, VHDL and Verilog sources

 

[7rots51]

HI Silvio
Thanks for your files.
I am waiting for your code.

 

[mr_ghz]

Hi 7rots51,

I attached 2 PDF's one with a multiplexer and one with the demultiplexer.
These schematics can be compiled in an Altera CPLD 3064 or similar. They
have to be understood as an example, how this work can be done. They
are functional, but there is potential to make it better (synchronous
counters, ...)
I hope this can help

Bye

 

[7rots51]

hi mr_ghz
Thanks for your technical help ,I saw the sch they are good ,I will test it.

bye