How can we perform Verilog simulation with and without intrinsic delay?

[ng8877]

For synch
ronous des
igns, the clock and control signal/data arrive at the same time step for Verilog without delay. What to do when there is a delay?
For example, a memory with synchronized write, at one cycle the clk, we and wd arrive at same time for no delay model. In reality, clk usually arrive early which mean data will be write in next cycle. how to solve this problem?

 

[BradtheRad]

Sometimes there's a layout or schematic at this forum having a cascade of invert-gates, each introducing a slight delay. Maybe a small capacitor (in role of integrator or differentiator) is put to use somehow.

There are ways of lengthening and shortening traces in order to alter timing slightly.

I think R&D teams must go through all kinds of contortions to solve real-life timing mismatches.