How can we pass a decimal value in the module Verilog

[appu1985]

I need to pass a value of o.o1 to module and it gets multiplied to some value inside.
Now if idefine it as a parameter it does not get implemented. what to do.

 

[imon]

I assume you are trying to write a *behavior* model, not RTL.
did you try declare a variable/parameter of real type, and assign 0.01 to it in a "initial" block?

 

[appu1985]

if i want write a synthesizable code then wat is required

 

[echo47]

In Verilog, a value such as 0.01 is called "real".

In a perfect world, a Verilog parameter can be real, but beware that many software tools, especially synthesis tools, have limited support for real. Which Verilog compiler are you using?

 

[appu1985]

I am using Xilinx ISE 9.1 can a real parameter be synthesized and for peforming operaions as Multiply , add , sub canbe performed simply by using the operators or we need to implement floating point arithmatic.

 

[echo47]

No, XST (the HDL synthesizer in ISE 9.1) doesn't synthesize Verilog "real" arithmetic. Maybe in some future version. It's a messy thing to do in a device that doesn't have floating-point math hardware.

ISE includes a configurable floating-point arithmetic core. Maybe you can use it. Open a Core Generator project and look under "Math Functions".
**broken link removed**

Or maybe you can redesign your algorithm to use integer arithmetic. The results will be a lot smaller and maybe faster than using floating-point cores.

 

[kishore2k4]

Maybe you can try using Fixed point arithmetic. If you are really interested in Hardware Arithemetic Circuits let me direct you to the book titled " Synthesis of Arithmetic Circuits - FPGA, ASIC and Embedded Systems", it is one hell of a comprehensive book on hardware number crunching, I am in the midst of completing it and am really enjoying it.

 

[appu1985]

can u provide me the ebook of it pls