Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
having clock skew helps in time budgeting in Partioned based design. where we can use the concept of something called as useful skew. if a design has some 4-5 then we can use the concept of useful skew to meet skew for the entire design.
It depends on whether it is positive or negative skew.....
Both has it own advantage.....
With positive skew....It is useful as we can increase the freq of the clock ...
And negative skew does not effect much as long it is the multiples of clk time period....
CTS : is the process where we try to minimise the skew in the design.
the clock skew can be minimised by the Post CTS optimization done by the tool, it resizes the clock buffers and the net lengths and balances the clock tree, most of these tools follow an algorithm which builds a binary tree for clock distribution.Binary tree can also be referred as Balanced H-tree.The skew that we are referring here is Local skew ( in one clock domain).
as the positive skew appears when the clock and the data flow in same directions,it helps in reducing the Tmax,hence actual Fmax can be Higher.( may raise race conditions)
as the negative skew appears when both the paths are in opposite directions, it increases the Tmax but unconditionally meets the hold conditions.
clock skew can also be minimised by manually editing ( make sure you use only clock buffer for optimisation) the nets when algorithm can't do it for any reason.
this is very important in power consumption reduction because if clk skew is not zero than all the clocks would not reach all the flops at the same time and the drop(IR) is less.
Please don bring power consumption topic into this discussion of clock skew...it isno way related....clock skew is something which happens naturally and dynamically....only we can do is to avoid negative effect due to it...u Cannot bring out adv from it because it is not in designer hands....
Clock skew is of both positive and negative. It helps in designs when we have problems with set up and hold time violations. Positive skew helps in reducing set up time while negative skew helps in reducing the hold time violations. But it has to be used effectively using different techniques like reverse clocking strategies in case of negative skew.
if u study any datasheet of fpga like spartan3 u can get the solution there to reduce the clock skew they explained how u can reduce or avoid clock skew.
we actually use delays
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.