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Layout and Circuit.
Use input diff. pair with large area MOSTs operating in weak or moderate inversion region. Use well matched load of diff. pair, proper sizing and strong inversion for current mirror.
One of source of systematic offset is difference of drain-source voltages of input diff. pair. U can eliminate this with proper biasing second stage or another technique which's related with CMRR and PSRR improvement technique in publications.
Use well matched layout (keywords: common centroid, dummy structures, placement, length of connections, metal coverage, temperature and machanical gradients and so on).
layout :
the differential input should go together and close to each other.
dont put them too close to avoid the parasitic capacitance between them.
and of course other techniques were already mentioned above.
using pin 1&5 in IC 741 we may reduce the input offset.
First pin no 2 & 3 are connected to ground.
In the output side (pin no 6) there may be some error voltages is present in the order of millivolts. To reduce this error voltage we have to connecting the potentiometer in b/w this two terminals (1 & 5) and adjust to get the output zero.
In layout, match is very important for low offset.
In circuit techniques, large area transistor will improve the match. Apart from this, dynamic cancellation techniques can solve this problem too,such as chopper, CDS.
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