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The System Generator for DSP tool is one of the industry's most popular DSP design tools for FPGAs. It automatically translates DSP systems developed using MATLAB® and Simulink® from The MathWorks into highly optimized VHDL and IP cores for Xilinx® FPGAs.
Designers can design and simulate a system using MATLAB, Simulink, and Xilinx library of bit/cycle-true models. Then it can greatly shorten the path from design concept to working hardware.
there is no need to change auto-generated code. but, sometimes there is a need to use project generated in sysgen as a module in bigger design (which for example employ multiple clock domains...)... only if so, you should change some of the autogenerated files.