Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how can i reduce the power

Status
Not open for further replies.

shelkerahul

Member level 4
Joined
Feb 8, 2005
Messages
79
Helped
10
Reputation
20
Reaction score
6
Trophy points
1,288
Location
Bangalore
Activity points
581
Hi,

As a backend designer, how can I reduce the POWER & IR drop? (I don’t want to make any changes in the code.)

Thanks in advance

Rahul
 

stormwolf

Advanced Member level 4
Joined
Jan 3, 2004
Messages
113
Helped
12
Reputation
24
Reaction score
0
Trophy points
1,296
Activity points
777
You can use power synthesis to reduce power. And power synthesis you can find at synopsys synthesis tools , but you need the power synthesis license.
 

shelkerahul

Member level 4
Joined
Feb 8, 2005
Messages
79
Helped
10
Reputation
20
Reaction score
6
Trophy points
1,288
Location
Bangalore
Activity points
581
Hi stormwolf


Thanks for your suggestion, but problem is, I am using MAGMA.
Can you give me a general idea, not related to any tool.

Thank you

Rahul
 

omid219

Advanced Member level 4
Joined
Feb 2, 2005
Messages
117
Helped
5
Reputation
10
Reaction score
1
Trophy points
1,298
Location
Malaysia
Activity points
988
power compiler of synopsys will optimize the power consumption, but may change the timing, BTW, you have to verify all aspects of design after optimization.
If you don't want to change the netlist, the only thing that you can do is doing a good floorplanning and reduce the wire length between data dependent blocks as much as possible to reduce IR drops. But I'm not sure that it reduces the power consumption.
 

peen1

Member level 2
Joined
Nov 2, 2004
Messages
47
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Activity points
495
There are techniques such as clock gating...which are very effective in reducing power consumption. Also minimize the use of buses as they hog power. Your DFT can get complicated if you use clock gatting.
 

sunms

Junior Member level 3
Joined
Feb 1, 2005
Messages
30
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
281
If you dont wanna change the codes,maybe you will have to refer to the tools to reduce the power.
Here is a document about clock_gating,you may read it and see how the tool is used to reduce power.
Hope it will help you.
I'm also using Magma,there's also tools in Magma to reduce power.
 

Thomson

Full Member level 3
Joined
Oct 15, 2004
Messages
181
Helped
4
Reputation
8
Reaction score
1
Trophy points
1,298
Activity points
2,400
There are a lot of ways to reduce the power dissipation:
(1) the systematic view: of cause, this is not your concern such as different algorithm and different architecture
(2) the circuit/logic design such as clock gating and good FSM coding styles to reduce the transitional rate of the circuit nodes
(3) the performance consideration such as low frequency/low voltage, please see the following equation:p=∑αcvf*f
(4) the techonological and device view such as dual-threshold devices: the low trheshold devices are applided for the high performace circuits while the high trheshold devices are used for the low performance circuits
(5) the floorplan view such as the global wire length reduction so as to reduce the parasitic resistance and capacitance
(6) the P&R strategy view such as the timing-driven strategy or the area-driven strategy
 

power-twq

Full Member level 6
Joined
Jun 10, 2005
Messages
373
Helped
8
Reputation
16
Reaction score
3
Trophy points
1,298
Activity points
4,550
you can put related logic together to minimize interconnect wire's length,

thus wire capacitance is reduced.




shelkerahul said:
Hi,

As a backend designer, how can I reduce the POWER & IR drop? (I don’t want to make any changes in the code.)

Thanks in advance

Rahul
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top