Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How can I put together two codes in Quartus

Status
Not open for further replies.
C

carla

Newbie
Joined
Jul 28, 2020
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
14
Hi, I wrote a code with a register file and a fsm. The less significant bits of the address 1 of the register file determinate the present state of the fsm and the less significant bits of the address 9 determinate the next state of the fsm. When I run the 2 code separately there are no error, but then I try to do the port map and I thing I did something wrong... could someone help me to find errors? the message errors are:

Code: 
Error (10028): Can't resolve multiple constant drivers for net "pres_state.idle" at top.vhd(76)
Error (10029): Constant driver at top.vhd(67)
Error (10028): Can't resolve multiple constant drivers for net "pres_state.clear" at top.vhd(76)
Error (10028): Can't resolve multiple constant drivers for net "pres_state.waitstatus" at top.vhd(76)
Error (10028): Can't resolve multiple constant drivers for net "pres_state.running" at top.vhd(76)
Error (10028): Can't resolve multiple constant drivers for net "pres_state.stopping" at top.vhd(76)
Error (12152): Can't elaborate user hierarchy "mealy:U2"
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 7 errors, 37 warnings
    Error: Peak virtual memory: 4698 megabytes
    Error: Processing ended: Tue Jul 28 13:40:15 2020
    Error: Elapsed time: 00:00:03
    Error: Total CPU time (on all processors): 00:00:03
Error (293001): Quartus II Full Compilation was unsuccessful. 9 errors, 37 warnings

the code is:

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity register_file is
port(
    datain      : in  std_logic_vector(31 downto 0);
    writeEnable : in  std_logic;
    regASel     : in  std_logic_vector(3 downto 0);  --Address
    regBSel     : in  std_logic_vector(3 downto 0);  --Address
    writeRegSel : in  std_logic_vector(3 downto 0);  --Address
    clk         : in  std_logic;
     reset       : in  std_logic;
    dataoutA    : out std_logic_vector(31 downto 0);
    dataoutB    : out std_logic_vector(31 downto 0)
    );
end register_file;

architecture behave of register_file is
type registerFile is array(0 to 15) of std_logic_vector(31 downto 0);
signal registers : registerFile;
begin
regFile : process (clk, reset)
begin
  if (reset = '0') then
    dataoutA <= (others => '0');
    dataoutB <= (others => '0');    
  elsif rising_edge(clk) then
    -- Lettura
    dataoutA <= registers(to_integer(unsigned(regASel)));
     dataoutB <= registers(to_integer(unsigned(regBSel)));
    -- Scrittura
    if writeEnable = '1' then
      registers(to_integer(unsigned(writeRegSel))) <= datain;
        if regASel = writeRegSel then
          dataoutA <= datain;
        end if;
          if regBSel = writeRegSel then
          dataoutB <= datain;
          end if;
    end if;
  end if;
end process;
end behave;


library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity mealy is
port (clk, reset: in std_logic;
       data_in     : in std_logic_vector (1 downto 0);
         data_out    : out std_logic;
         regASel     : in  std_logic_vector(3 downto 0);  --Address
       regBSel     : in  std_logic_vector(3 downto 0);
         dataoutA    : in std_logic_vector(2 downto 0);
        dataoutB    : in std_logic_vector(1 downto 0)
         );
end mealy;
architecture behave of mealy is
type state_value is (idle, clear, waitstatus, running, stopping);
signal pres_state, next_state: state_value;

begin
-- FSM register
statereg: process (clk, reset)
begin
if (reset = '0') then
  pres_state <= idle;
elsif (clk'event and clk ='1') then
  pres_state <= next_state;
end if;
end process statereg;
-- FSM combinational block
fsm: process (pres_state, data_in)
begin
  if(regASel <= "1001" and regBSel <= "0001") then
     if (dataoutA(2 downto 0) <= "001") then
       pres_state <= idle;
       if (dataoutB(1 downto 0)<= "00") then
         next_state <= clear;
         else
          null;
         end if;
     elsif (dataoutA(2 downto 0) <= "001") then
       pres_state <= clear;
       if (dataoutB(1 downto 0)<= "00") then
          next_state <= clear;
       elsif (dataoutB(1 downto 0)<= "01") then
          next_state <= waitstatus;
       else
          null;
         end if;
     elsif (dataoutA(2 downto 0) <= "010") then
       pres_state <= waitstatus;
        if (dataoutB(1 downto 0)<= "10") then
         next_state <= running;
      else
         null;
        end if;
     elsif (dataoutA(2 downto 0) <= "011") then
       pres_state <= running;
      if (dataoutB(1 downto 0)<= "10") then
         next_state <= running;
      elsif (dataoutB(1 downto 0)<= "11") then
         next_state <= stopping;
      else
         null;
        end if;
    elsif (dataoutA(2 downto 0) <= "100") then
       pres_state <= stopping;
       if (dataoutB(1 downto 0)<= "11") then
         next_state <= stopping;
      elsif (dataoutB(1 downto 0)<= "00") then
         next_state <= clear;
      else
         null;
       end if;
     end if;
  end if;
end process fsm;
outputs: process (pres_state, data_in)
begin
  if(regASel <= "1001" and regBSel <= "0001") then
    if (dataoutA(2 downto 0) <= "000") then
      pres_state <= idle;
      if (dataoutB(1 downto 0)<= "00") then
        data_out <= '0' ;
     else
       null;
      end if;
    elsif (dataoutA(2 downto 0) <= "001") then
      pres_state <= clear;
      if (dataoutB(1 downto 0)<= "00") then
         data_out <= '1';
      elsif (dataoutB(1 downto 0)<= "01") then
         data_out <= '0';
      else
        null;
      end if;
    elsif (dataoutA(2 downto 0) <= "010") then
      pres_state <= waitstatus;
      if (dataoutB(1 downto 0)<= "01") then
         data_out <= '0';
     else
       null;
     end if;
    elsif (dataoutA(2 downto 0) <= "011") then
      pres_state <= running;
      if (dataoutB(1 downto 0)<= "10") then
         data_out <= '1';
      elsif (dataoutB(1 downto 0)<= "11") then
         data_out <= '0';
      else
       null;
      end if;
    elsif (dataoutA(2 downto 0) <= "100") then
      pres_state <= stopping;
      if (dataoutB(1 downto 0)<= "11") then
        data_out <= '1';
      elsif (dataoutB(1 downto 0)<= "00") then
         data_out <= '0';
      else
        null;
      end if;
    end if;
end if;
end process outputs;
end behave;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is
port (clock, rst: in std_logic; data_in: in std_logic_vector(31 downto 0);
    datain      : in  std_logic_vector(31 downto 0);
    writeEnable : in  std_logic;
    writeRegSel : in  std_logic_vector(3 downto 0);  --Address
    clk         : in  std_logic;
     reset       : in  std_logic;
     data_out    : out std_logic);
end top;

architecture structural of top is
component mealy is
  port (clock, rst  : in std_logic;
       data_in     : in std_logic_vector (1 downto 0);
         data_out    : out std_logic);
end component;

component register_file is
  port(
    datain      : in  std_logic_vector(31 downto 0);
    writeEnable : in  std_logic;
    regASel     : in  std_logic_vector(3 downto 0);  --Address
    regBSel     : in  std_logic_vector(3 downto 0);  --Address
    writeRegSel : in  std_logic_vector(3 downto 0);  --Address
    clk         : in  std_logic;
     reset       : in  std_logic;
    dataoutA    : out std_logic_vector(31 downto 0);
    dataoutB    : out std_logic_vector(31 downto 0)
    );
  end component;

  signal regASel, regBSel: std_logic_vector(3 downto 0);
  signal dataoutA, dataoutB: std_logic_vector(31 downto 0);
 
begin
       
U1 : register_file
      port map (datain (31 downto 0), writeEnable, regASel(3 downto 0), regBSel(3 downto 0),
        writeRegSel (3 downto 0), clk, reset, dataoutA(31 downto 0), dataoutB(31 downto 0));
U2 : mealy
      port map (data_in(1 downto 0) => dataoutB(1 downto 0), clock => clock, rst => rst, data_out => data_out);

end structural;
 
Last edited:

the error is quite self-explanatory: you can't have two drivers to the same signal.
 

I understand, but I don't know how to resolve it and make the project work as it shold. Do you have any suggestions?
 

You have three different process that are all making assignments to press_state in the code posted. You have no code that is assigning next_state, which is what I think you meant to put in the two combinational process. You should also need to combine the two combinational process as those will also result in multiple driver errors.

Don't drive signals by more than one process (that includes driving from a continous assignment or an instantiation).
 

Like has been pointed out, the two combinational processes can be combined in one process. One good way that would make the coding easier is by embedding IF STATEMENTS within CASE STATEMENT. In the combinational process, the case statement should track the current state and the IF statements should track the inputs.

Make assignments to outputs and next state within the IF statements.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top