achaleus
Member level 5
Hello everyone,
I am using ISE 14.7 for synthesis and Questasim 10.0c for simulation. I am doing post synthesis simulation to find out simulation and synthesis mismatch. ISE elaborated all hierarchy files into a single file for e.g. \instance1/my_signal[15:0]. The signals generated are so vast and I unable to add particular set of signals to the waveform window(I am adding all signals to the wave window) and its taking days for 1/10th of the simulation. It is difficult to find out the present value of my_signal.
My question is how can I monitor this hierarchical signal. gives you
if I use
$monitor("current iteration is %d",PicoSim.FPGA.UserWrapper.UserModuleTop.\mymodule_INST1/iteration );
or
$monitor("current iteration is %d",PicoSim.FPGA.UserWrapper.UserModuleTop.\mymodule_INST1/iteration[15:0] );
giving
Unresolved reference to 'UserModuleTop' in PicoSim.FPGA.UserWrapper.UserModuleTop.
Vinay
I am using ISE 14.7 for synthesis and Questasim 10.0c for simulation. I am doing post synthesis simulation to find out simulation and synthesis mismatch. ISE elaborated all hierarchy files into a single file for e.g. \instance1/my_signal[15:0]. The signals generated are so vast and I unable to add particular set of signals to the waveform window(I am adding all signals to the wave window) and its taking days for 1/10th of the simulation. It is difficult to find out the present value of my_signal.
My question is how can I monitor this hierarchical signal. gives you
if I use
$monitor("current iteration is %d",PicoSim.FPGA.UserWrapper.UserModuleTop.\mymodule_INST1/iteration );
or
$monitor("current iteration is %d",PicoSim.FPGA.UserWrapper.UserModuleTop.\mymodule_INST1/iteration[15:0] );
giving
Unresolved reference to 'UserModuleTop' in PicoSim.FPGA.UserWrapper.UserModuleTop.
Vinay