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How can I join CADENCE or SYNOPSYS

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devop

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I graduated half a year ago.I'm work in a design house and do a lot of jobs here:DC for synthesis ,SOC_E for P&R ,design some analog blocks........
a lot of things but did't focus on one point.
But what I really want to be is a application engineer in cadence or synopsys ,what should i prepare?focus on one thing and become a expert on it ?or know all the design flow ?
And according the website statement of cadence or synopsys,most of the supporter have more than 5 years experence.I don't want to be a member of them 5years later......
what should I do from now on?can anyone give some advice?
 

For Cadence tool you dont need so much time, just some couple of months (of course some advanced things you can lear later), but to become a good designer you need much more. If you only build some previously speciifed analog blocks than you need 2-3 years. For more time the most important is that you will be able to make design faster and without errors, which in translation to your managers means lot of money. That is the reason because they like to hear for experience of 5+yrs...
 

do you mean that a AE must be a good design first?so I must devote to the design either in analog or digital?
 

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