how can i get the output of regulator stable?

[zrffxx]

hello,everyone.
I got a problem.
As in the picture,there is a regulator in the red block which is used to generate 1.8V voltage for the other circuits' power supply.When it is alone,it works well and has 30mA driving ability.But when the vco or any oscillator is attached as shown in the picture,the output of regulator has ripples when the oscillator is oscillating.
Why?The vco's frequency is up to 100Mhz. I guess that the voltage of oscillator's output swithed too fast that the output of the regulator cannot follow it.Am I right?So I should increase the opamp's GBW in the regulator?What factor decide the GBW?Equal to the oscillator's maximum frequency?How could I solve this problem?
Thank you very much!

 

[wonbef]

maybe EMI.

I think a better plan and layout of PCB needed, and a filtering cap needed.

 

[Lucifre]

Hi zrffxx, i am attaching the document that describes the basics of the voltage regulators. My guess is that the voltage regulator you are using does not have pass device ( darlington BJT transistor) this device provides current to the load so that it is not drawn from the OPAMP (op amp alone mey not be capable of providing adequate currents)... second advice is that there is something wrong with the mosfet you are using (check its datasheet and see hot it bevaes with pulses of varying frequencies) and the third thing you can do is to put some capacitors before oscillator to improve transient response. the fourth advice is buy a LM 317 and drop building your own regulator altogether (cheaper)

best regards

Added after 3 minutes:

i guess it won't let me post that document. send me your e-mail so i can send it to thruogh regular e-mail

 

[DenisMark]

Do u use decoupling capacitor at the output of regulator? I don't see one at the picture.
For decrease output ripple due oscillation u need: decoupling capacitor at the output of regulator; low resistance pass device, use nmos at the output of regulator if "power" voltage is enough. The GBW and slew rate of the error amplifier affect on recovery response of regulator.
See

for get advace in LDO theory.

 

[zrffxx]

Thank you for your replies.
Firstly, The circuit shown above is integrated circuit in only one chip that i'am designing now .So there isn't problem about PCB layout.But thank you all the same.
Secondly,to Lucifre,my email is :zrf_pku@hotmail.com
Thirdly,to DenisMark,the link you give me:

cannot be connected.Could you send the article to my email?
Thankyou!

 

[bcl]

I don't see and series inductor nor shunt caps to block or short out any signals/noise from the ring oscillator coupling back into the regulator?

 

[Siniša]

I would add bypass cap in parallel with feedback resistor. It would make circuit little faster, but bypass cap and series resistor or inductor are needed as well.

 

[wjlzhx]

you should add a cap at the output of 1.8V

I think it's the ony method ,when you need a large current.

good luck!!

 

[jonashat]

The circuit you have is a two stage amplifier (opamp + PMOS amplifier) adding a cap at the output will hurt your stability.

 

[zrffxx]

i have added the compensation cap at the 1.8v output node,the ripple gets small,but still exist.

 

[bcl]

Z=1/(j*ω*C), so larger capacitance provides lower impedance to ground to short out the ripple.

 

[mswug]

it is a full integrated LDO, so do you compensate your LDO with miller capacitor or DFC?

 

[gelo]

Try to check the datasheet of the LDO ic and there is a load capacitor that is suggested in order to remove the "ringing" at the source voltage of the ring oscillator

 

[derekqiao]

Please recaculate the poles in different loading current conditions because this is a two-stage amplifier. You have phase margin issue.

 

[renwl]

i have added the compensation cap at the 1.8v output node,the ripple gets small,but still exist.

what's the capacitor value? what's the type?
what's the amplitude of ripple now?
can you upload some pics about the measurement?

 

[VSMVDD]

ripple from the regulation stage

its probably your probe that gets noisy

scopes are really high gain

so ... ignore this ripple

infact ignore any ripple lower than 20mv level

it matters not


a tip to completely remove ripple is just to add a battery

but i beleve even if you measure this youll find a ripple

also watch for things like fluresent tubes in your work room even normal lamps will generate an electro magnetic field

a tip is to make sure they have a suppressor

also check your fridge and other domestic appliances

and use a plug block that has a filter
make sure the scope is earthed some engineers remove the earth

check you have a good house earth by running another one to a ground peg sunk atleast 5 ft down

then try again

 

[hung_wai_ming@hotmail.com]

Ripples always there in LDO design when loading changes. Now your loading is changing with high frequency as well, so LDO cannot repond fast enough and only way to minimize it is to add output cap as stabilization cap BOTH for your LDO design needs and for ripple reduction. Anyway, there's a spec for transient output variation when loading changes. You should be able to get a number less than 0.5-1% for max. loading change. Otherwise, your LDO has design issues