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hi,
in INL &DNL testing you must have use histogram testing and so you must use as many sample as you have resolution in your ADC.
example, a linear ramp (in actual practice, a triangular waveform is used)which slightly exceeds both ends of the range of the ADC is a popular histogram test signal.
you can use a periodic ramp signal that is ramp proportional to your adc resolution and sampler frequency . for example if your INL need .05LSB (20 hit for each code )and you have 14-bit,100MSPS ADC ,so you have total NO of sample 20*2^14=327680 sample and sampling frequency 100 MSPS , this implies that the input ramp should make a full-scale transition in 3.3 ms.
I know the CDS test ,but in ADS or cadence , it takes so long time ,isn't it ? especially my ADC sample frequency is low 5Ms/s,Is there any simple way to do the test ?
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