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How can I get a flatten netlist?

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flatten spice netlist

I hava a hierarchy schematic. But I need the flatten spice netlist to foundry. How can I get it?

The design environment is Cadence 4.4.5.

Thans a lot.
 

piao

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spice netlist flattening

When you genereating netlist, you can generate it from Analog Artist, in its netlisting menu, you can choose hierachy or flatten

BR
 

okguy

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flatten netlist

Or you can give them the extracted netlist from calibre or dracula or whatever you use 8)
 

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netlist flatten

piao said:
When you genereating netlist, you can generate it from Analog Artist, in its netlisting menu, you can choose hierachy or flatten

BR

I can not find the menu of netlist in Analog Artist. Please tell me about this menu.

Thank you!!
 

chinito

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what is flattened netlist

hierarchy --> flatten to get flattened objects. Then go to 'create netlist'.
 

Hughes

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spice netlist flattener

Question said:
piao said:
When you genereating netlist, you can generate it from Analog Artist, in its netlisting menu, you can choose hierachy or flatten

BR

I can not find the menu of netlist in Analog Artist. Please tell me about this menu.

Menu:
Setup / Environment...
Choose Netlist Type in the Environment Options form
 

xuel

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script to flatten spice netlist

to huges

sorry i cant find Netlist Type in the Environment Options form
 

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netlist hierarchy flatten

xuel said:
to huges

sorry i cant find Netlist Type in the Environment Options form

U must change the simulator to hspiceS first.
 

kaisopos

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hi all,

i m a newbie and i have the same problem (flattening my netlist).

Here's the exact problem: I synthesized my verilog design using RC and I wanna feed the synthesized netlist to Primetime. For some reason "read_verilog synthesized.v" cannot read a hierarchical netlist, since all modules become black boxes. But, if I declare as my top module a module that does not reference other modules, then primetime reads it without complaints. So I assume that the hierarchy is responsible for these black boxes. Long story short, I wanna flatten my synthesized gate-level netlist so that I only have 1 module. Is there any easy (newbie-friendly) way to do so? I dont have access to magma tools; just RC, cadence encounter, synopsys primetime.

thanks thanks
-Kostas
 

RBB

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Most tools, including Primetime can handle hierarchical netlists, so you shouldn't need to flatten it. However I'm sure RC has an ungroup command.

You can flatten via: ungroup -flatten -all
but like I said, you shouldn't have to for primetime.
 

jrrk

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hi all,

i m a newbie and i have the same problem (flattening my netlist).

Here's the exact problem: I synthesized my verilog design using RC and I wanna feed the synthesized netlist to Primetime. For some reason "read_verilog synthesized.v" cannot read a hierarchical netlist, since all modules become black boxes. But, if I declare as my top module a module that does not reference other modules, then primetime reads it without complaints. So I assume that the hierarchy is responsible for these black boxes. Long story short, I wanna flatten my synthesized gate-level netlist so that I only have 1 module. Is there any easy (newbie-friendly) way to do so? I dont have access to magma tools; just RC, cadence encounter, synopsys primetime.

thanks thanks
-Kostas

Dear kaisopos,
No doubt you have solved this problem now. But just for posterity, I don't like to see an incorrect assumption in the forum. The reason for the black boxes is because Primetime a.k.a. pt_shell requires the cell library which contains the timing and functionality of the cells which is stored in a .lib file for your technology. When compiled it is stored in a .db file. The compiled file must be from the same or older version of Primetime. The source file can only be read in with LibraryCompiler license and would use the read_lib command. Once the .db or .lib is read the hierarchical netlist will read OK without generating black boxes. If for some reason you still require a flat netlist and you have DesignCompiler license you can use the ungroup -all -flatten command in dc_shell to get a flat netlist but this is not recommended unless you have a very small chip because the files and processing time become huge. pt_shell does not have the capability to manipulate netlists, it strictly a timing engine.
 

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