How can I find Rise/fall time of xilinx FPGA?

[jay_ec_engg]

How can I find rise and fall time of output signals from XILINX FPGA ? Will it generate any file after synthesis which will provide this sinformation ?

 

[hill]

My method is using digital oscilloscope (Yokogawa DL1540).

 

[Johnson]

on Xilinx main datasheet, which is available on site! The fields on datasource CD is not complete!

 

[jay_ec_engg]

I have to do timing analysis for output signals from spartan-3 fpga before actual testing (before board comes). So i cant use oscilloscope. Datasheet also doesnt have rise/fall time information. Can I get this info from any of the report file after synthesis ?

 

[au_sun]

u get rise time and fall time information from the REPORT after XST synthesis,
the report contains MAX frequency, and all other timing estimates for the I/O signals of the design

 

[power-twq]

The rise and fall time is determined by fpga output's drive ability and

capacitance loading (pcb trace, etc.). you may not find it after synthesis.

but you can find it after PCB simulation.

best regards

How can I find rise and fall time of output signals from XILINX FPGA ? Will it generate any file after synthesis which will provide this sinformation ?