Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How can I find Rise/fall time of xilinx FPGA?

Status
Not open for further replies.

jay_ec_engg

Full Member level 3
Joined
Jun 19, 2004
Messages
155
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Location
India
Activity points
1,581
How can I find rise and fall time of output signals from XILINX FPGA ? Will it generate any file after synthesis which will provide this sinformation ?
 

hill

Full Member level 5
Joined
Jun 17, 2004
Messages
278
Helped
10
Reputation
20
Reaction score
1
Trophy points
1,298
Activity points
2,334
My method is using digital oscilloscope (Yokogawa DL1540).
 

Johnson

Advanced Member level 2
Joined
Oct 4, 2004
Messages
520
Helped
28
Reputation
56
Reaction score
7
Trophy points
1,298
Activity points
3,613
on Xilinx main datasheet, which is available on site! The fields on datasource CD is not complete!
 

jay_ec_engg

Full Member level 3
Joined
Jun 19, 2004
Messages
155
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,296
Location
India
Activity points
1,581
I have to do timing analysis for output signals from spartan-3 fpga before actual testing (before board comes). So i cant use oscilloscope. Datasheet also doesnt have rise/fall time information. Can I get this info from any of the report file after synthesis ?
 

au_sun

Full Member level 2
Joined
Aug 5, 2004
Messages
147
Helped
15
Reputation
30
Reaction score
4
Trophy points
1,298
Activity points
1,184
u get rise time and fall time information from the REPORT after XST synthesis,
the report contains MAX frequency, and all other timing estimates for the I/O signals of the design
 

power-twq

Full Member level 6
Joined
Jun 10, 2005
Messages
373
Helped
8
Reputation
16
Reaction score
3
Trophy points
1,298
Activity points
4,550
The rise and fall time is determined by fpga output's drive ability and

capacitance loading (pcb trace, etc.). you may not find it after synthesis.

but you can find it after PCB simulation.

best regards





jay_ec_engg said:
How can I find rise and fall time of output signals from XILINX FPGA ? Will it generate any file after synthesis which will provide this sinformation ?
 
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top