Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I think different designer will design his USB core with different ways. Especial registers will use especial bits. Such as write-clear, read-clear, or hardware-clear.
So the testbench from other usb cores is same only in interface signals timing. And the hub and device is differents.
So I think you should write those patterns by yourselves.
If you have the interesting, you can find the simple example in opencore. But those patterns are not complete.
I think the interface of USB testbench is bus level or PHY level, for example: dwusbd. Because I want the testbench can simulate a host to send FULL and LOW speed signals both, and can check the result automatically. This is difficult and requires lots of time.
The testbench for OpenCore usb_func 1.1 is simple for me to complete my work.
For business core, it's impossible to upload here.
I think you can write many basic task. From send J and send K to write task for transfer. Then write a script to product the test pattern automatically.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
