moh_monem43
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how can i execute this program?
---------------my_package-----------------------
library ieee;
use ieee.std_logic_1164.all;
package my_package is
constant limit : integer := 255;
procedure sort (signal in1, in2 : in integer range 0 to limit;
signal min, max : out integer range 0 to limit);
end my_package;
package body my_package is
procedure sort ( signal in1, in2 : in integer range 0 to limit;
signal min, max : out integer range 0 to limit) is
begin
if (in1 > in2) then
max <= in1;
min <= in2;
else
max <= in2;
min <= in1;
end if;
end sort;
end my_package;
-----------------------------------------------------------------------------
---------------min_max1---------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.my_package.all;
entity min_max1 is
generic (limit : integer := 255);
port ( ena : in bit;
inp1, inp2 : in integer range 0 to limit;
min_out, max_out : out integer range 0 to limit);
end min_max1;
architecture my_architecture of min_max1 is
begin
process(ena)
begin
if (ena = '1') then sort (inp1, inp2, min_out, max_out);
end if;
end process;
end my_architecture;
-----------------------------------------------------------------------
if i make this program in one file, compilation ok. but when divided this program into two file (my_package + min_max1), compilation not succeed.
can any one explain the steps for implementing this program (in details).
note: this is example 11.10 in circuit design with VHDL (pedroni).
thanks.
---------------my_package-----------------------
library ieee;
use ieee.std_logic_1164.all;
package my_package is
constant limit : integer := 255;
procedure sort (signal in1, in2 : in integer range 0 to limit;
signal min, max : out integer range 0 to limit);
end my_package;
package body my_package is
procedure sort ( signal in1, in2 : in integer range 0 to limit;
signal min, max : out integer range 0 to limit) is
begin
if (in1 > in2) then
max <= in1;
min <= in2;
else
max <= in2;
min <= in1;
end if;
end sort;
end my_package;
-----------------------------------------------------------------------------
---------------min_max1---------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.my_package.all;
entity min_max1 is
generic (limit : integer := 255);
port ( ena : in bit;
inp1, inp2 : in integer range 0 to limit;
min_out, max_out : out integer range 0 to limit);
end min_max1;
architecture my_architecture of min_max1 is
begin
process(ena)
begin
if (ena = '1') then sort (inp1, inp2, min_out, max_out);
end if;
end process;
end my_architecture;
-----------------------------------------------------------------------
if i make this program in one file, compilation ok. but when divided this program into two file (my_package + min_max1), compilation not succeed.
can any one explain the steps for implementing this program (in details).
note: this is example 11.10 in circuit design with VHDL (pedroni).
thanks.