how can I evaluate number gates used in my design

[tybhsl]

After I synthesis my code with design compiler, it is reported as total cell area. And how can I know the number gates used in my design? Thanks!

 

[elektor]

Hi,

You can have a look at size two-input NAND gate in your library documentation.
Next you must divide your area by size this NAND gate.

Regards
Elektor

 

[maxsnail]

under .18 process one two-inputs nand gate about 3 um * 3um,
report your whole era and divide it

 

[elektor]

Hi,

Under UMC 0.18 process NAND gate has 12.2 um2 not 9 um2 as you said above

Elektor

 

[geconom]

I believe you get not only total area but also details about what library components are used. If your design is not too big, you can search your library documentation and find the exact size (in transistor count) of your design. Otherwise, the algorithm in the previous post is the best you can get.

 

[tybhsl]

Thanks!
Here, I get a TMSC standard cell library in which I fail to find the area unit, say as the following:
"cell (NAND2X1) {
cell_footprint : nand2;
area : 17.2800;
pin(A) {
direction : input;
capacitance : 0.00790;
}
"
can you tell me what's the default unit of "area : 17.2800"? Is it um^2?
and afterward, I synthesis a file using this library and get a repert of the total cell area without any unit as well. What's the default unit here? Thank you very much!

 

[suituse]

yes, 17.28um^2 , the typical area for a nand2 gate in 0.25um process

 

[jinruan]

i think area report by DC has no practical means,
you can find the true area after layout.

 

[they]

i think area report by DC has no practical means,
you can find the true area after layout.

You mean the area reported by DC will be very much different with the one synthesized after layout?

 

[eda_wiz]

yes.. because DC can reliably say only the cell area. the interconnect area and finally the die size depends on how the P n R is done..

rgds

 

[arm946es_softcore]

taking 2inputs nand gate with x1 drive strength as a gate
then, total area / area of nand2x1.

you should set wire load to auto select

 

[haosg]

you can get gate-count with (total area / NAND2X1 area).
or write a tcl to report hier area.

Added after 40 seconds:

sorry it is " write a tcl to report instance count".

 

[jinruan]

and during VDSM optimization in backend design, size of cell maybe changed, so the area report by DC is only a estimate value