How can i design vco in 90nm?

[junfun]

I want to design a vco at 2.5GHz in 90nm.
I have to simulator tt 25 degree but the corners(ff 0 degree in vdd+10% and ss 100 degree in vdd-10%) was fail.
Delay cell in vco was symmetrical load.
How can i improve it?

Regards

 

[sandip_micro]

Hello dear..
i am also trying to design a Symmetrical type load Delay cell in 0.18u.Maneatis delay cell PDF u might have read.shall I send the link.
http://www.truecircuits.com/images/pdfs/maneatis96b.pdf
main thing is there is a design procedure for designing such tyle of Delay Cells.
One more link from waterloo uni is:
www.asic.uwaterloo.ca/files/cmos_ic_team/pll/documentation/delay_cell_ryan.pdf

Added after 1 minutes:

If u ahve any PDF regarding the Symmetrical type Load VCO design please send me.

 

[pankajdudulwar]

Which architecture u are using for VCO. If ur using architecture other than cross coupled then u might be facing this problem(I suppose). Can u please tell about the archotecture

 

[pfd001]

I want to design a vco at 2.5GHz in 90nm.
I have to simulator tt 25 degree but the corners(ff 0 degree in vdd+10% and ss 100 degree in vdd-10%) was fail.
Delay cell in vco was symmetrical load.
How can i improve it?

Regards

How about the gain of your delay cell? the gain of the delay cell should have enough margin for corners. If you use a fixed bias current for simulation, you can use a current from the bandgap, it will give you better results.